Searched refs:Src0Regs (Results 1 - 2 of 2) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1669 SmallVector<Register, 2> Src0Regs(OpdMapper.getVRegs(1));
1674 assert(Src0Regs.empty() && Src1Regs.empty());
1679 assert(Src0Regs.size() == Src1Regs.size() &&
1680 (Src0Regs.empty() || Src0Regs.size() == 2));
1687 if (Src0Regs.empty())
1688 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
1690 setRegsToType(MRI, Src0Regs, HalfTy);
1701 .addUse(Src0Regs[0])
1706 .addUse(Src0Regs[
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp2412 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; local
2414 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2426 MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2428 MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2431 {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2707 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; local
2709 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2716 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
3645 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; local
3649 Src0Regs, Src0LeftoverReg
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