/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | DetectDeadLanes.cpp | 112 void PutInWorklist(unsigned RegIdx) { argument 113 if (WorklistMembers.test(RegIdx)) 115 WorklistMembers.set(RegIdx); 116 Worklist.push_back(RegIdx); 363 unsigned RegIdx = Register::virtReg2Index(Reg); local 364 DefinedByCopy.set(RegIdx); 365 PutInWorklist(RegIdx); 496 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { 507 unsigned RegIdx = Worklist.front(); local 542 unsigned RegIdx = Register::virtReg2Index(Reg); local [all...] |
H A D | SplitKit.h | 322 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains: 324 /// 1. No entry - the value is not mapped to Edit.get(RegIdx). 326 /// Edit.get(RegIdx). Each value is represented by a minimal live range at 328 /// of RegIdx in RegAssign. 340 /// getLRCalc - Return the LRCalc to use for RegIdx. In spill mode, the 343 LiveRangeCalc &getLRCalc(unsigned RegIdx) { argument 344 return LRCalc[SpillMode != SM_Partition && RegIdx != 0]; 361 /// defValue - define a value in RegIdx from ParentVNI at Idx. 369 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx, 372 /// forceRecompute - Force the live range of ParentVNI in RegIdx t [all...] |
H A D | SplitKit.cpp | 456 VNInfo *SplitEditor::defValue(unsigned RegIdx, argument 463 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); 472 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); 474 // This was the first time (RegIdx, ParentVNI) was mapped, and it is not 493 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { argument 494 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; 506 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); 540 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { 553 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); 627 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, argument 538 buildCopy(unsigned FromReg, unsigned ToReg, LaneBitmask LaneMask, MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) argument 877 unsigned RegIdx = AssignI.value(); local 1132 unsigned RegIdx; local 1271 unsigned RegIdx = RegAssign.lookup(V->def); local 1286 unsigned RegIdx = RegAssign.lookup(V->def); local 1309 unsigned RegIdx; member in struct:ExtPoint 1335 unsigned RegIdx = RegAssign.lookup(Idx); local 1480 unsigned RegIdx = RegAssign.lookup(ParentVNI->def); local [all...] |
H A D | LiveVariables.cpp | 85 LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { argument 86 assert(Register::isVirtualRegister(RegIdx) && 88 VirtRegInfo.grow(RegIdx); 89 return VirtRegInfo[RegIdx];
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.cpp | 203 unsigned RegIdx = State.getFirstUnallocated(RegList); local 208 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) 209 State.AllocateReg(RegList[RegIdx++]); 247 unsigned RegIdx = State.getFirstUnallocated(RegList); local 249 if (RegIdx >= RegList.size()) 252 It.convertToReg(State.AllocateReg(RegList[RegIdx++]));
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H A D | ARMISelLowering.cpp | 4037 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); local 4038 if (RegIdx != array_lengthof(GPRArgRegs)) 4039 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRAsmPrinter.cpp | 115 unsigned RegIdx = ByteNumber / BytesPerReg; local 116 assert(RegIdx < NumOpRegs && "Multibyte index out of range."); 118 Reg = MI->getOperand(OpNum + RegIdx).getReg();
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 863 struct RegIdxOp RegIdx; member in union:__anon5236::MipsOperand::__anon5237 878 Op->RegIdx.Index = Index; 879 Op->RegIdx.RegInfo = RegInfo; 880 Op->RegIdx.Kind = RegKind; 881 Op->RegIdx.Tok.Data = Str.data(); 882 Op->RegIdx.Tok.Length = Str.size(); 892 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); 893 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); 895 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CollectLOH.cpp | 517 int RegIdx = mapRegToGPRIndex(LI.PhysReg); local 518 if (RegIdx >= 0) 519 LOHInfos[RegIdx].OneUser = true;
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveVariables.h | 273 VarInfo &getVarInfo(unsigned RegIdx);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelDAGToDAG.h | 35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
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H A D | MipsSEISelDAGToDAG.cpp | 78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { 79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); 842 SDValue RegIdx = Node->getOperand(2); local 844 getMSACtrlReg(RegIdx), MVT::i32); 875 SDValue RegIdx = Node->getOperand(2); local 878 getMSACtrlReg(RegIdx), Value);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86SpeculativeLoadHardening.cpp | 2244 unsigned RegIdx = Log2_32(RegBytes); local 2245 assert(RegIdx < 4 && "Unsupported register size"); 2257 if (RC == NOREXRegClasses[RegIdx]) 2263 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]);
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H A D | X86FastISel.cpp | 2644 unsigned RegIdx = X86::sub_16bit; local 2645 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx);
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H A D | X86ISelLowering.cpp | [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 1556 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); local 1558 if (RegIdx != array_lengthof(ArgGPRs) && RegIdx % 2 == 1)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 2129 unsigned RegIdx = RegNum / AlignSize; local 2136 if (RegIdx >= RC.getNumRegs()) 2139 return RC.getRegister(RegIdx);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 1666 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); local 1667 if (RegIdx == ArgVGPRs.size()) { 1674 unsigned Reg = ArgVGPRs[RegIdx]; 1688 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); local 1689 if (RegIdx == ArgSGPRs.size()) 1692 unsigned Reg = ArgSGPRs[RegIdx];
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6647 unsigned RegIdx = 3; local 6655 RegIdx = 4; 6657 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && 6659 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || 6661 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
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