Searched refs:PartTy (Results 1 - 6 of 6) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp190 Type *PartTy = PartVT.getTypeForEVT(Ctx); local
191 LLT PartLLT = getLLTForType(*PartTy, DL);
198 SplitArgs.emplace_back(ArrayRef<Register>(PartReg), PartTy, OrigArg.Flags); local
222 LLT PartTy) {
229 const unsigned PartSize = PartTy.getSizeInBits();
231 if (SrcTy.isVector() && !PartTy.isVector() &&
248 LLT BigTy = getMultipleType(PartTy, NumRoundedParts);
218 unpackRegsToOrigType(MachineIRBuilder &B, ArrayRef<Register> DstRegs, Register SrcReg, LLT SrcTy, LLT PartTy) argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp82 Type *PartTy = PartVT.getTypeForEVT(Context); local
86 ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*PartTy, DL)),
87 PartTy, OrigArg.Flags};
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizerHelper.h158 /// \p PartRegs must be registers of type \p PartTy.
160 /// If \p ResultTy does not evenly break into \p PartTy sized pieces, the
163 LLT PartTy, ArrayRef<Register> PartRegs,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DSROA.cpp3859 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8);
3861 auto *PartPtrTy = PartTy->getPointerTo(AS);
3863 PartTy,
3994 auto *PartTy = Type::getIntNTy(Ty->getContext(), PartSize * 8);
3995 auto *LoadPartPtrTy = PartTy->getPointerTo(LI->getPointerAddressSpace());
3996 auto *StorePartPtrTy = PartTy->getPointerTo(SI->getPointerAddressSpace());
4006 PartTy,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp196 LLT ResultTy, LLT PartTy,
208 if (PartTy.isVector())
215 unsigned PartSize = PartTy.getSizeInBits();
2937 // Split the load/store into PartTy sized pieces starting at Offset. If this
2939 // of ValRegs should be PartTy. Returns the next offset that needs to be
2941 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2944 unsigned PartSize = PartTy.getSizeInBits();
2957 Register Dst = MRI.createGenericVirtualRegister(PartTy);
195 insertParts(Register DstReg, LLT ResultTy, LLT PartTy, ArrayRef<Register> PartRegs, LLT LeftoverTy, ArrayRef<Register> LeftoverRegs) argument
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2741 // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
2742 MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign) local
2745 allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());

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