Searched refs:DefInst (Results 1 - 10 of 10) sorted by relevance
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFixupVectorISel.cpp | 96 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg()); local 97 switch (DefInst->getOpcode()) { 101 Worklist.push_back(&DefInst->getOperand(1)); 104 if (DefInst->getNumOperands() != 5) 106 Worklist.push_back(&DefInst->getOperand(1)); 107 Worklist.push_back(&DefInst->getOperand(3)); 113 if (DefInst->getOperand(2).getSubReg() != AMDGPU::NoSubRegister) 115 BaseReg = DefInst->getOperand(2).getReg(); 116 if (DefInst->getOperand(3).getSubReg() != AMDGPU::NoSubRegister) 118 IndexReg = DefInst [all...] |
H A D | SIPeepholeSDWA.cpp | 530 const MachineInstr *DefInst = Def.getParent(); local 531 if (!TII->isFoldableCopy(*DefInst)) 534 const MachineOperand &Copied = DefInst->getOperand(1);
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H A D | SIInstrInfo.cpp | 6459 auto *DefInst = MRI.getVRegDef(RSR.Reg); 6460 while (auto *MI = DefInst) { 6461 DefInst = nullptr; 6470 DefInst = MRI.getVRegDef(RSR.Reg); 6478 DefInst = MRI.getVRegDef(RSR.Reg); 6481 if (!DefInst)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFMISimplifyPatchable.cpp | 105 MachineInstr *DefInst = I->getParent(); local 106 unsigned Opcode = DefInst->getOpcode(); 120 const MachineOperand &ImmOp = DefInst->getOperand(2); 130 const MachineOperand &Opnd = DefInst->getOperand(0); 135 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) 136 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) 138 DefInst->eraseFromParent(); 268 MachineInstr *DefInst local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | EarlyCSE.cpp | 520 Instruction *DefInst = nullptr; member in struct:__anon5635::EarlyCSE::LoadValue 528 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), 1115 if (InVal.DefInst != nullptr && 1123 InVal.DefInst, Inst))) { 1124 Value *Op = getOrCreateResult(InVal.DefInst, Inst->getType()); 1127 << " to: " << *InVal.DefInst << '\n'); 1208 if (InVal.DefInst && 1209 InVal.DefInst == getOrCreateResult(Inst, InVal.DefInst->getType()) && 1215 InVal.DefInst, Ins [all...] |
H A D | NewGVN.cpp | 3945 auto *DefInst = dyn_cast_or_null<Instruction>(Def); 3946 if (DefInst && AllTempInstructions.count(DefInst)) { 3947 auto *PN = cast<PHINode>(DefInst);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCBranchCoalescing.cpp | 462 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); local 463 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) {
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonCopyToCombine.cpp | 414 MachineInstr *DefInst = LastDef[Reg]; local 415 if (!DefInst) 417 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) 422 MachineBasicBlock::iterator It(DefInst); 433 PotentiallyNewifiableTFR.insert(DefInst);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | MemorySSA.cpp | 265 Instruction *DefInst = MD->getMemoryInst(); local 266 assert(DefInst && "Defining instruction not actually an instruction"); 270 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { 300 ModRefInfo I = AA.getModRefInfo(DefInst, UseCall); 305 if (auto *DefLoad = dyn_cast<LoadInst>(DefInst)) 309 ModRefInfo I = AA.getModRefInfo(DefInst, UseLoc);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegAllocFast.cpp | 303 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { 304 if (DefInst.getParent() != MBB || ++C >= Limit) {
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