/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 119 : FP(P), TRI(T) {} 120 const FlowPattern &FP; member in struct:__anon2847::PrintFP 127 OS << "{ SplitB:" << PrintMB(P.FP.SplitB) 128 << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) 129 << ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:" 130 << PrintMB(P.FP.FalseB) 131 << ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; 159 FlowPattern &FP); 167 bool isValid(const FlowPattern &FP) const; 170 bool isProfitable(const FlowPattern &FP) cons 215 matchFlowPattern(MachineBasicBlock *B, MachineLoop *L, FlowPattern &FP) argument 775 updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP) argument 825 convert(const FlowPattern &FP) argument 1012 simplifyFlowGraph(const FlowPattern &FP) argument [all...] |
H A D | HexagonExpandPredSpillCode.cpp | 244 unsigned FP = MI->getOperand(0).getReg(); local 245 assert(FP == QST.getRegisterInfo()->getFrameRegister() && 259 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 268 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 282 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2); 291 unsigned FP = MI->getOperand(1).getReg(); local 292 assert(FP == QST.getRegisterInfo()->getFrameRegister() && 303 .addReg(FP) 313 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 323 HEXAGON_RESERVED_REG_2).addReg(FP) [all...] |
/freebsd-11.0-release/contrib/binutils/opcodes/ |
H A D | alpha-opc.c | 350 #define FP(oo,fff) FP_(oo,fff), FP_MASK 667 { "itofs", FP(0x14,0x004), CIX, { RA, ZB, FC } }, 668 { "sqrtf/c", FP(0x14,0x00A), CIX, ARG_FPZ1 }, 669 { "sqrts/c", FP(0x14,0x00B), CIX, ARG_FPZ1 }, 670 { "itoff", FP(0x14,0x014), CIX, { RA, ZB, FC } }, 671 { "itoft", FP(0x14,0x024), CIX, { RA, ZB, FC } }, 672 { "sqrtg/c", FP(0x14,0x02A), CIX, ARG_FPZ1 }, 673 { "sqrtt/c", FP(0x14,0x02B), CIX, ARG_FPZ1 }, 674 { "sqrts/m", FP(0x14,0x04B), CIX, ARG_FPZ1 }, 675 { "sqrtt/m", FP( 347 #define FP macro [all...] |
/freebsd-11.0-release/sys/arm/include/ |
H A D | stack.h | 53 #define FP 11 macro
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/freebsd-11.0-release/contrib/llvm/lib/Target/ |
H A D | TargetSubtargetInfo.cpp | 27 const InstrStage *IS, const unsigned *OC, const unsigned *FP) 28 : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) { 22 TargetSubtargetInfo( const Triple &TT, StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
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/freebsd-11.0-release/etc/rc.d/ |
H A D | ipsec | 50 ${ipsec_program} -FP
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/freebsd-11.0-release/contrib/libc++/src/ |
H A D | chrono.cpp | 119 typedef steady_clock::rep (*FP)(); typedef in class:chrono::steady_clock 122 FP 137 static FP fp = init_steady_clock();
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/freebsd-11.0-release/contrib/llvm/include/llvm/Analysis/ |
H A D | RegionPass.h | 117 Pass *FP = static_cast<Pass *>(PassVector[N]); 118 return FP;
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/freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 43 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, 53 MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, 91 Reserved.set(MSP430::FP); 116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); 125 Offset += 2; // Skip the saved FP 160 return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP;
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H A D | MSP430FrameLowering.cpp | 67 // Save FP into the appropriate stack slot... 69 .addReg(MSP430::FP, RegState::Kill); 71 // Update FP with the new base value... 72 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) 78 I->addLiveIn(MSP430::FP); 136 // pop FP. 137 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); 159 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); 292 // Create a frame entry for the FP register that must be saved. 297 "Slot for FP registe [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/InstPrinter/ |
H A D | WebAssemblyInstPrinter.cpp | 112 static std::string toString(const APFloat &FP) { argument 115 if (FP.isNaN()) 116 assert((FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) || 117 FP.bitwiseIsEqual( 118 APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) && 121 auto Written = FP.convertToHexString(
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/freebsd-11.0-release/sys/arm/arm/ |
H A D | db_trace.c | 88 state->registers[SP], state->registers[FP]); 92 ~((1 << SP) | (1 << FP) | (1 << LR) | (1 << PC)); 162 state.registers[FP] = ctx->pcb_regs.sf_r11; 182 state.registers[FP] = (uint32_t)__builtin_frame_address(0);
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/freebsd-11.0-release/tools/regression/ipsec/ |
H A D | ipsec6.t | 66 setkey -FP 101 setkey -FP
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H A D | ipsec.t | 66 setkey -FP 101 setkey -FP
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/freebsd-11.0-release/contrib/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 44 const InstrStage *IS, const unsigned *OC, const unsigned *FP) 47 ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) { 39 MCSubtargetInfo( const Triple &TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 185 // Reserve FP if this function should have a dedicated frame pointer register. 190 Reserved.set(Mips::FP); 292 return TFI->hasFP(MF) ? (IsN64 ? Mips::FP_64 : Mips::FP) : 308 unsigned FP = Subtarget.isGP32bit() ? Mips::FP : Mips::FP_64; local 317 if (!MF.getRegInfo().canReserveReg(FP))
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 115 Reserved.set(AArch64::FP); 147 case AArch64::FP: 177 // large enough that referencing from the FP won't result in things being 204 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; 222 // FP when there's no better way to access it (SP or base pointer). 242 /// reference would be better served by a base register other than FP 274 // FP, LR, X19-X28, D8-D15. 64-bits each. 287 // The FP is only available if there is no dynamic realignment. We 290 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) 417 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP [all...] |
/freebsd-11.0-release/sys/crypto/des/ |
H A D | des_enc.c | 162 FP(r,l); 274 FP(r,l); 294 FP(r,l);
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/freebsd-11.0-release/contrib/llvm/lib/IR/ |
H A D | LegacyPassManager.cpp | 283 FPPassManager *FP = static_cast<FPPassManager *>(PassManagers[N]); 284 return FP; 1472 FunctionPass *FP = getContainedPass(Index); local 1473 AnalysisResolver *AR = FP->getResolver(); 1518 FunctionPass *FP = getContainedPass(Index); local 1519 FP->dumpPassStructure(Offset + 1); 1520 dumpLastUses(FP, Offset+1); 1538 FunctionPass *FP = getContainedPass(Index); local 1541 dumpPassInfo(FP, EXECUTION_MSG, ON_FUNCTION_MSG, F.getName()); 1542 dumpRequiredSet(FP); [all...] |
/freebsd-11.0-release/contrib/gdb/gdb/ |
H A D | sparc-stub.c | 113 I0, I1, I2, I3, I4, I5, FP, I7, enumerator in enum:regnames 608 *ptr++ = hexchars[FP >> 4]; 609 *ptr++ = hexchars[FP & 0xf]; 611 ptr = mem2hex(sp + 8 + 6, ptr, 4, 0); /* FP */
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/freebsd-11.0-release/crypto/openssl/crypto/des/ |
H A D | des_enc.c | 148 FP(r, l); 254 FP(r, l); 274 FP(r, l);
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/freebsd-11.0-release/contrib/llvm/include/llvm/MC/ |
H A D | MCSubtargetInfo.h | 59 const unsigned *OC, const unsigned *FP);
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/freebsd-11.0-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetSubtargetInfo.h | 58 const unsigned *OC, const unsigned *FP);
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/freebsd-11.0-release/contrib/llvm/tools/bugpoint/ |
H A D | ExtractFunction.cpp | 269 Constant *FP = CS->getOperand(1); local 270 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(FP)) 272 FP = CE->getOperand(0); 273 if (Function *F = dyn_cast<Function>(FP)) {
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/freebsd-11.0-release/sys/cddl/dev/dtrace/arm/ |
H A D | dtrace_isa.c | 83 state.registers[FP] = (uint32_t)__builtin_frame_address(0); 152 state.registers[FP] = (uint32_t)__builtin_frame_address(0);
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