/freebsd-10.2-release/sys/arm/arm/ |
H A D | cpufunc_asm_arm11.S | 47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 49 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 50 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 60 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 84 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 85 mcr p1 [all...] |
H A D | cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 52 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */ 57 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 62 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 70 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 76 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
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H A D | cpufunc_asm_arm11x6.S | 69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ 83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 118 mcr p1 [all...] |
H A D | cpufunc_asm_fa526.S | 43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */ 44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */ 45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */ 46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */ 48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */ 51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */ 63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */ 71 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */ 79 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/ 85 mcr p1 [all...] |
H A D | cpufunc_asm_armv6.S | 52 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 54 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 70 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 81 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 82 mcr p15, 0, r0, c7, c10, 0 /* Clean D cache */ 83 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 101 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 115 mcr p1 [all...] |
H A D | cpufunc_asm_arm10.S | 49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 60 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 65 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 88 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 89 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 93 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 104 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 113 mcr p1 [all...] |
H A D | cpufunc_asm_xscale.S | 148 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 149 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ 156 mcr p15, 0, r0, c2, c0, 0 159 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ 162 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 179 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 180 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 188 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 193 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ 198 mcr p1 [all...] |
H A D | cpufunc_asm_armv5_ec.S | 60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 110 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 128 mcr p1 [all...] |
H A D | cpufunc_asm_armv5.S | 50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 76 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 77 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 81 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 92 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 101 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 105 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 126 mcr p1 [all...] |
H A D | cpufunc_asm_pj4b.S | 43 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 47 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 48 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 53 mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */ 58 mcr p15, 0, r0, c7, c5, 6 /* flush entrie branch target cache */ 63 mcr p15, 0, r0, c7, c5, 7 /* flush branch target cache by VA */ 80 mcr p15, 1, r0, c15, c1, 0 90 mcr p15, 1, r0, c15, c1, 1 99 mcr p15, 1, r0, c15, c2, 0 109 mcr p1 [all...] |
H A D | cpufunc_asm_xscale_c3.S | 148 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ 160 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */ 169 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 186 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */ 188 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 195 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 208 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ 209 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 216 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 229 1: mcr p1 [all...] |
H A D | cpufunc_asm.S | 108 mcr p15, 0, r0, c1, c0, 0 114 mcr p15, 0, r0, c3, c0, 0 182 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 184 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 186 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 187 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 190 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 191 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
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H A D | cpufunc_asm_arm9.S | 48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 97 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 106 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 127 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 144 mcr p1 [all...] |
H A D | cpufunc_asm_sheeva.S | 50 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ 54 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ 55 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ 60 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 62 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 64 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 93 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ 94 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ 106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 136 mcr p1 [all...] |
H A D | cpufunc_asm_armv7.S | 77 mcr CP15_TTBR0(r0) 80 mcr CP15_TLBIALLIS 82 mcr CP15_TLBIALL 92 mcr CP15_TLBIALLIS 93 mcr CP15_BPIALLIS 95 mcr CP15_TLBIALL 96 mcr CP15_BPIALL 107 mcr CP15_TLBIMVAAIS(r0) 108 mcr CP15_BPIALLIS 110 mcr CP15_TLBIMV [all...] |
H A D | cpu_asm-v6.S | 49 mcr CP15_DCIALL 59 mcr CP15_CSSELR(r0) /* set cache level */ 80 2: mcr CP15_DCISW(r3) /* invalidate line */ 95 mcr CP15_CSSELR(r0) 104 mcr CP15_DCIALL 114 mcr CP15_CSSELR(r0) /* set cache level */ 135 2: mcr CP15_DCISW(r3) /* invalidate line */ 150 mcr CP15_CSSELR(r0) 158 mcr CP15_DCCIALL 167 1: mcr CP15_CSSEL [all...] |
H A D | locore-v6.S | 105 mcr CP15_SCTLR(r7) 108 mcr CP15_ICIALLU 229 mcr CP15_TTBR0(r0) /* Set TTB */ 231 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */ 235 mcr CP15_DACR(r0) 245 mcr CP15_NMRR(r0) 247 mcr CP15_TLBIALL /* Flush TLB */ 259 mcr CP15_SCTLR(r0) 262 mcr CP15_TLBIALL /* Flush TLB */ 263 mcr CP15_BPIAL [all...] |
H A D | locore-v4.S | 156 mcr p15, 0, r2, c1, c0, 0 224 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 225 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 229 mcr p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 234 mcr p15, 0, r0, c3, c0, 0 248 mcr p15, 0, r0, c1, c0, 0 416 mcr p15, 0, r2, c1, c0, 0 435 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 436 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 439 mcr p1 [all...] |
H A D | swtch.S | 165 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 197 mcr p15, 0, r5, c13, c0, 4 209 mcr p15, 0, r6, c13, c0, 3 244 mcr p15, 0, r1, c13, c0, 4 280 mcr p15, 0, r9, c13, c0, 3 349 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
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/freebsd-10.2-release/sys/dev/uart/ |
H A D | uart_dev_ns8250.h | 39 uint8_t mcr; member in struct:ns8250_softc
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/freebsd-10.2-release/sys/arm/include/ |
H A D | asm.h | 232 #define ISB mcr CP15_CP15ISB 233 #define DSB mcr CP15_CP15DSB 234 #define DMB mcr CP15_CP15DMB 235 #define WFI mcr CP15_CP15WFI 237 #define ISB mcr CP15_CP15ISB 238 #define DSB mcr CP15_CP15DSB /* DSB and DMB are the */ 239 #define DMB mcr CP15_CP15DSB /* same prior to v6.*/
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/freebsd-10.2-release/sys/arm/mv/armadaxp/ |
H A D | mptramp.S | 36 mcr p15, 0, r0, c7, c7, 0
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/freebsd-10.2-release/usr.sbin/bhyve/ |
H A D | uart_emul.c | 103 uint8_t mcr; /* Modem control register (R/W) */ member in struct:uart_softc 346 if ((sc->mcr & MCR_LOOPBACK) != 0) { 384 if (sc->mcr & MCR_LOOPBACK) { 428 sc->mcr = value & 0x1F; 431 if (sc->mcr & MCR_LOOPBACK) { 436 if (sc->mcr & MCR_RTS) 438 if (sc->mcr & MCR_DTR) 440 if (sc->mcr & MCR_OUT1) 442 if (sc->mcr & MCR_OUT2) 538 reg = sc->mcr; [all...] |
/freebsd-10.2-release/sys/dev/vte/ |
H A D | if_vte.c | 1232 uint16_t mcr; local 1237 mcr = CSR_READ_2(sc, VTE_MCR0); 1238 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1240 mcr |= MCR0_FULL_DUPLEX; 1243 mcr |= MCR0_FC_ENB; 1251 mcr |= MCR0_FC_ENB; 1254 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1587 uint16_t mcr; local 1590 mcr = CSR_READ_2(sc, VTE_MCR1); 1591 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESE 1807 uint16_t mcr; local 1834 uint16_t mcr; local 1947 uint16_t mchash[4], mcr; local [all...] |
/freebsd-10.2-release/sys/dev/ubsec/ |
H A D | ubsec.c | 646 struct ubsec_mcr *mcr; local 655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 1777 struct ubsec_mcr *mcr; local 1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1792 mcr->mcr_pkts = htole16(1); 1793 mcr->mcr_flags = 0; 1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1795 mcr->mcr_ipktbuf.pb_addr = mcr 2147 struct ubsec_mcr *mcr; local 2349 struct ubsec_mcr *mcr; local 2547 struct ubsec_mcr *mcr; local 2763 ubsec_dump_mcr(struct ubsec_mcr *mcr) argument [all...] |