Searched refs:Reads (Results 1 - 10 of 10) sorted by relevance
/freebsd-10.0-release/contrib/llvm/utils/TableGen/ |
H A D | CodeGenSchedule.h | 70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence 118 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may 126 /// that mapped the itinerary class to the variant Writes or Reads. 133 IdxVec Reads; member in struct:llvm::CodeGenSchedClass 148 return ItinClassDef == IC && Writes == W && Reads == R; 335 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; 348 const IdxVec &Reads) const; 393 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
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H A D | CodeGenSchedule.cpp | 188 // Reads don't current have sequence records, but it can be added later. 388 IdxVec &Writes, IdxVec &Reads) const { 393 findRWs(ReadDefs, Reads, true); 515 IdxVec Writes, Reads; 517 findRWs((*I)->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); 522 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); 563 for (IdxIter RI = SC.Reads.begin(), RE = SC.Reads.end(); RI != RE; ++RI) 575 IdxVec Reads; 577 Writes, Reads); [all...] |
H A D | SubtargetEmitter.cpp | 889 IdxVec Reads = SCI->Reads; local 904 Reads.clear(); 906 Writes, Reads); 917 Writes, Reads); 998 for (unsigned UseIdx = 0, EndIdx = Reads.size(); 1001 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
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/freebsd-10.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBundle.h | 154 /// Reads - One of the operands read the virtual register. This does not 156 bool Reads; member in struct:llvm::MachineOperandIteratorBase::VirtRegInfo 177 /// Reads - Read or a super-register is read. 178 bool Reads; member in struct:llvm::MachineOperandIteratorBase::PhysRegInfo
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/freebsd-10.0-release/contrib/llvm/lib/CodeGen/ |
H A D | EarlyIfConversion.cpp | 273 SmallVector<unsigned, 8> Reads; local 299 Reads.push_back(Reg); 302 while (!Reads.empty()) 303 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
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H A D | MachineInstrBundle.cpp | 266 RI.Reads = true; 306 PRI.Reads = true;
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H A D | RegisterCoalescer.cpp | 906 bool Reads, Writes; local 907 tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); 911 if (DstInt && !Reads && SubIdx) 912 Reads = DstInt->liveAt(LIS->getInstructionIndex(UseMI)); 922 MO.setIsUndef(!Reads);
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H A D | MachineBasicBlock.cpp | 1172 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive; 1201 return (Analysis.Reads) ?
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H A D | InlineSpiller.cpp | 1192 if (RI.Reads)
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/freebsd-10.0-release/contrib/llvm/lib/Transforms/Vectorize/ |
H A D | LoopVectorize.cpp | 2677 AliasMap Reads; local 2722 Reads.insert(std::make_pair(Ptr, LD)); 2727 if (ReadWrites.size() == 1 && Reads.size() == 0) { 2750 for (MI = Reads.begin(), ME = Reads.end(); MI != ME; ++MI) { 2782 // Now that the pointers are in two lists (Reads and ReadWrites), we 2841 for (MI = Reads.begin(), ME = Reads.end(); MI != ME; ++MI) {
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