Searched refs:MTCTR (Results 1 - 6 of 6) sorted by relevance
/freebsd-10.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.cpp | 181 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
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H A D | PPCISelLowering.h | 107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a 108 /// MTCTR instruction. 109 MTCTR, enumerator in enum:llvm::PPCISD::NodeType
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H A D | PPCCTRLoops.cpp | 727 TII->get(isPPC64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(CountReg,
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H A D | PPCAsmPrinter.cpp | 939 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12)); 994 OutStreamer.EmitInstruction(MCInstBuilder(PPC::MTCTR).addReg(PPC::R12));
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H A D | PPCISelDAGToDAG.cpp | 1271 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
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H A D | PPCISelLowering.cpp | 632 case PPCISD::MTCTR: return "PPCISD::MTCTR"; 3246 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair 3317 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps, 4103 // Check if this is an indirect call (MTCTR/BCTRL). 4118 // mean the MTCTR instruction must use R12; it's easier to model this 4462 // not mean the MTCTR instruction must use R12; it's easier to model this as 6240 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
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