/barrelfish-master/usr/eclipseclp/Kernel/src/ |
H A D | sch_util.c | 81 int instruction = 0; local 106 instruction |= SCHSET_MAX2PUBLISH; 107 instruction |= SCHSET_MAXVALUE & tmp->val.nint; 114 instruction |= SCHSET_ROOT2BOTTOM; 116 instruction |= SCHSET_BOTTOM2ROOT; 118 instruction |= SCHSET_LEFT2RIGHT; 120 instruction |= SCHSET_RIGHT2LEFT; 122 instruction |= SCHSET_RESETCOUNTS; 124 instruction |= SCHSET_IDLING; 126 instruction | 579 int i, instruction = * (int *) infoval; local [all...] |
/barrelfish-master/tools/fastmodels/ |
H A D | cache.c | 29 write_csselr_el1(int level, int instruction) { argument 32 * RES0 | level | instruction 34 uint64_t x= (instruction & 0x1) | ((level & 0x7) << 1); 65 /* Invalidate all instruction caches to point of unification. */
|
/barrelfish-master/usr/eclipseclp/documents/internal/kernel/ |
H A D | kernel.tex | 328 \index{put instruction} 329 \index{get instruction} 340 located on the shared heap. The instruction just loads a pointer 413 \item[PP] program (code) pointer, points to next abstract machine instruction. 580 \index{get instruction} 594 \index{get instruction} 627 \index{get instruction} 648 \index{read instruction} 677 preceding get/write/read_structure/list instruction has constructed the 680 \index{write instruction} [all...] |
H A D | debugger.tex | 254 Debug_call instruction: 257 Call instruction: 286 retry/trust instruction: 319 is caught by Restore_bp instruction, which does not contain the checks 321 instruction before (or after) the Restore_bp:
|
H A D | runtime.tex | 405 get_constant/put_constant instruction. This means that all instances
|
/barrelfish-master/usr/eclipseclp/Shm/src/ |
H A D | lock.S | 50 * Some SPARC implementations don't have the swap instruction 149 ; LDCWS instruction requires 16-byte alignment
|
/barrelfish-master/usr/eclipseclp/Kernel/lib/ |
H A D | asm.pl | 57 % A single instruction is a term whose functor specifies the instruction 58 % and whose arguments are the instruction operands, e.g. 90 % <try refs> switches for try_parallel instruction 138 desc:html(" Assembles the WAM instruction WAMCode into the current ECLiPSe session 140 each element representing one WAM instruction. The format of the WAMCode 164 desc:html(" Assembles the WAM instruction WAMCode into the current ECLiPSe session 167 instruction. The format of the WAMCode is the same as that generated by 196 representing one WAM instruction. The format of the WAMCode is the same 235 element representing one WAM instruction [all...] |
H A D | stat.pl | 32 % If SEPIA is compiled with the PRINTAM option, virtual instruction 57 % pretty-prints the instruction statistics. 68 % pretty-prints the instruction pair statistics. 161 writeln('SEPIA abstract machine instruction statistics'), 304 writeln('SEPIA abstract machine instruction pair statistics'), 377 writeln('SEPIA abstract machine instruction pair counter'),
|
H A D | tracer_tty.pl | 481 trace_mode(13, []), % abstract instruction tracing on/off
|
H A D | fd.pl | 746 % A true which is not optimized away so that we have a call instruction which
|
/barrelfish-master/lib/openssl-1.0.0d/crypto/ |
H A D | sparccpuid.S | 41 ! Following is V9 "rd %ccr,%o0" instruction. However! V8 245 ! Probe and instrument VIS1 instruction. Output is number of cycles it
|
/barrelfish-master/doc/022-armv8/ |
H A D | report.tex | 90 ARMv8 discards some long-standing features of the ARM instruction set: 95 instruction-set changes, however challenging to the systems programmer, are 517 indicating the instruction set to be used (much as is already done with 953 user-level execution address. In ARMv8, the \texttt{eret} instruction 964 longer be the target of a load instruction, but can only be loaded via a 971 multiple) instruction, there is no way to load the program counter with an 989 indirect jumps (load to PC) back to the instruction set. 995 8--29 for ARMv8 corresponds to the single \texttt{ldmia} instruction on lines 996 9 for ARMv7 --- one instruction is now 18, on the thread-switch critical path! 1000 monitor) instruction i [all...] |
/barrelfish-master/lib/cxx/unwind/ |
H A D | UnwindRegistersSave.S | 787 @ T1 does not have a non-cpsr-clobbering register-zeroing instruction. 794 @ . the pc (r15) cannot be in the list in an STM instruction
|
H A D | UnwindRegistersRestore.S | 652 @ . the pc (r15) and lr (r14) cannot both be in the list in an LDM instruction 676 @ So, generate the instruction using the corresponding coprocessor mnemonic.
|
/barrelfish-master/lib/acpica/source/tools/examples/ |
H A D | extables.c | 422 WBINVD instruction is operational (V1) : 0
|
/barrelfish-master/usr/eclipseclp/icparc_solvers/ilog/ |
H A D | fd_min_max.pl | 388 % A true which is not optimized away so that we have a call instruction which
|
/barrelfish-master/lib/openssl-1.0.0d/crypto/bn/asm/ |
H A D | pa-risc2.s | 15 ; by Gerry Kane for information on the instruction set architecture.
|
H A D | pa-risc2W.s | 9 ; by Gerry Kane for information on the instruction set architecture.
|
/barrelfish-master/doc/026-device-queues/ |
H A D | devif.tex | 131 instruction reordering and other optimizations. Currently X86 and Sparc can be 136 of the buffer. TSO is still a very strict memory model and only allows limited instruction
|
/barrelfish-master/usr/eclipseclp/documents/userman/ |
H A D | umsusing.tex | 504 will then wait for a further instruction: either a \notation{<CR>}
|
/barrelfish-master/doc/003-hake/ |
H A D | Hake.tex | 195 later). This list has a single element, the instruction to built an
|
/barrelfish-master/doc/017-arm/ |
H A D | ARM.tex | 667 In-Order and O3. The first two are simple one-cycle-per-instruction
|
/barrelfish-master/lib/tommath/ |
H A D | tommath.tex | 2626 is required for the product. In x86 terms for example, this means using the MUL instruction. 4273 then a x86 multiplier could produce the 62-bit product and use the ``shrd'' instruction to perform a double-precision right shift. The proof
|