/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/ |
H A D | clock.c | 209 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 218 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, 227 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, 236 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, 245 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 254 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/ |
H A D | clock.c | 209 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 218 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, 227 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, 236 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, 245 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 254 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/include/mach/ |
H A D | regs-clock.h | 28 #define S5P_CLK_DIV0 S5P_CLKREG(0x20) macro 126 #define ARM_CLK_DIV S5P_CLK_DIV0
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/include/mach/ |
H A D | regs-clock.h | 28 #define S5P_CLK_DIV0 S5P_CLKREG(0x20) macro 126 #define ARM_CLK_DIV S5P_CLK_DIV0
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/include/mach/ |
H A D | regs-clock.h | 37 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/include/mach/ |
H A D | regs-clock.h | 37 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6442/include/mach/ |
H A D | regs-clock.h | 41 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/ |
H A D | clock.c | 78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, 87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, 134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, 153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 979 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/ |
H A D | regs-clock.h | 41 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/ |
H A D | clock.c | 78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 }, 87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 }, 134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, 144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 }, 153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, 979 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5p6440/ |
H A D | clock.c | 239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 }, 248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, 257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, 266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pv210/include/mach/ |
H A D | regs-clock.h | 41 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6440/ |
H A D | clock.c | 239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 }, 248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 }, 257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 }, 266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/include/mach/ |
H A D | regs-clock.h | 41 #define S5P_CLK_DIV0 S5P_CLKREG(0x300) macro
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/arch/arm/mach-s5pc100/ |
H A D | clock.c | 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, 136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
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/asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pc100/ |
H A D | clock.c | 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, 136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, 145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, 154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, 163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
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