| /linux-master/arch/mips/kvm/ |
| H A D | msa.S | 93 .macro kvm_restore_msa_upper wr, off, base
98 insert_d \wr, 1
101 insert_w \wr, 2
103 insert_w \wr, 3
106 insert_w \wr, 2
108 insert_w \wr, 3
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| /linux-master/arch/sparc/include/asm/ |
| H A D | visasm.h | 23 297: wr %g0, FPRS_FEF, %fprs; \
26 wr %g0, 0, %fprs;
43 297: wr %o5, FPRS_FEF, %fprs;
46 wr %o5, 0, %fprs;
58 " 298: wr %%g0, 0, %%fprs\n"
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| H A D | winmacro.h | 52 wr %scratch, 0x0, %y;
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| /linux-master/arch/sparc/kernel/ |
| H A D | etrap_32.S | 121 wr %g2, 0x0, %wim
215 wr %g2, 0x0, %wim
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| H A D | etrap_64.S | 54 wr %g0, 0, %fprs
84 wr %g3, 0x0, %asi
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| H A D | fpu_traps.S | 25 wr %g0, FPRS_FEF, %fprs
187 wr %g7, 0, %gsr
192 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
383 wr %g0, 0, %fprs
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| H A D | hvtramp.S | 95 wr %g0, 0, %fprs
96 wr %g0, ASI_P, %asi
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| H A D | ivec.S | 35 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
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| H A D | sun4v_ivec.S | 132 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
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| H A D | trampoline_32.S | 47 wr %g1, 0x0, %psr ! traps off though
52 wr %g1, 0x0, %wim
56 wr %g3, 0x0, %tbr
71 wr %g1, PSR_ET, %psr ! traps on
101 wr %g1, 0x0, %psr ! traps off though
106 wr %g1, 0x0, %wim
111 wr %g1, 0x0, %tbr
132 wr %g1, PSR_ET, %psr ! traps on
160 wr %g1, 0x0, %psr ! traps off though
165 wr
[all...] |
| H A D | tsb.S | 567 wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
590 wr %g2, 0x0, %asi
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| H A D | una_asm_64.S | 13 wr %o3, 0, %asi
46 wr %o4, 0x0, %asi
71 wr %o4, 0, %asi
128 wr %o5, 0x0, %asi
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| H A D | wof.S | 111 wr %glob_tmp, 0x0, %wim ! set new %wim, this is safe now
122 wr %t_psr, 0x0, %psr ! restore condition codes in %psr
148 wr %glob_tmp, 0x0, %wim ! Now it is safe to set new %wim
191 wr %t_psr, 0x0, %psr
253 wr %t_psr, PSR_ET, %psr
286 wr %t_psr, 0x0, %psr
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| H A D | wuf.S | 93 wr %twin_tmp1, 0x0, %wim /* Make window 'I' invalid */
122 wr %t_psr, 0x0, %psr
180 wr %t_wim, 0x0, %wim
188 wr %t_psr, PSR_ET, %psr ! enable traps
214 wr %t_psr, 0x0, %psr
300 wr %t_psr, 0x0, %psr
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| /linux-master/arch/sparc/lib/ |
| H A D | GENbzero.S | 44 wr %o4, 0x0, %asi
87 wr %o4, 0x0, %asi
109 wr %o5, 0x0, %asi
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| H A D | M7memset.S | 190 wr %g0, ASI_STBIMRU_P, %asi
282 wr %g3, 0x0, %asi ! restored saved %asi
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| H A D | Memcpy_utils.S | 11 wr %g0, ASI_AIUS, %asi
16 wr %g0, ASI_AIUS, %asi
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| H A D | NG2memcpy.S | 18 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
20 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
22 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
23 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
186 wr %g0, ASI_AIUS, %asi
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| H A D | NG4memcpy.S | 23 wr %g0, FPRS_FEF, %fprs; \
29 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
32 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
105 wr %g0, 0x80, %asi
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| H A D | NGbzero.S | 45 wr %o4, 0x0, %asi
72 wr %g7, 0x0, %asi
89 wr %o4, 0x0, %asi
111 wr %o5, 0x0, %asi
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| H A D | NGpage.S | 22 wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
57 wr %g3, 0x0, %asi
68 wr %g0, ASI_BLK_INIT_QUAD_LDD_P, %asi
106 wr %g3, 0x0, %asi
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| H A D | U3memcpy.S | 16 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs; \
18 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
20 #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs
21 #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs
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| H A D | udivdi3.S | 52 wr %g0, 0, %y
190 wr %g0,%o1,%y ! SPARC has 0-3 delay insn after a wr
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| /linux-master/arch/sparc/mm/ |
| H A D | swift.S | 62 wr %g3, 0x0, %psr
100 wr %g1, 0x0, %psr
128 wr %g3, 0x0, %psr
166 wr %g1, 0x0, %psr
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| /linux-master/arch/sparc/power/ |
| H A D | hibernate_asm.S | 65 wr %g0, ASI_PHYS_USE_EC, %asi
120 wr %g1, %g0, %asi
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