Searched refs:t0 (Results 1 - 25 of 233) sorted by path

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/linux-master/arch/alpha/include/uapi/asm/
H A Dregdef.h7 #define t0 $1 /* temporary registers (caller-saved) */ macro
H A Dswab.h27 __u64 t0, t1, t2, t3; local
29 t0 = __kernel_inslh(x, 7); /* t0 : 0000000000AABBCC */
31 t1 |= t0; /* t1 : 000000CCDDAABBCC */
33 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */
35 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
/linux-master/arch/alpha/lib/
H A Dev6-stxcpy.S54 t0 == the first destination word for masking back in
63 mskql t0, a1, t0 # U : assemble the first output word
65 or t0, t3, t1 # E : (stall)
69 t0 == the first destination word for masking back in
98 ldq_u t0, 0(a0) # L : Latency=3
103 zap t0, t8, t0 # E : clear dst bytes <= null
104 or t0, t1, t1 # E : (stall)
123 xor a0, a1, t0 #
[all...]
H A Dev6-stxncpy.S22 * t0 = last word written
62 t0 == the first destination word for masking back in
71 mskql t0, a1, t0 # U : assemble the first output word
73 or t0, t3, t0 # E : (stall)
82 t0 == a source word not containing a null. */
90 stq_u t0, 0(a0) # L :
95 ldq_u t0, 0(a1) # L :
97 cmpbge zero, t0, t
[all...]
H A Dstxcpy.S43 t0 == the first destination word for masking back in
51 mskql t0, a1, t0 # e0 : assemble the first output word
53 or t0, t3, t1 # e0 :
57 t0 == the first destination word for masking back in
83 ldq_u t0, 0(a0) # e0 :
87 zap t0, t8, t0 # e0 : clear dst bytes <= null
88 or t0, t1, t1 # e1 :
103 xor a0, a1, t0 # e
[all...]
H A Dstxncpy.S22 * t0 = last word written
51 t0 == the first destination word for masking back in
59 mskql t0, a1, t0 # e0 : assemble the first output word
61 or t0, t3, t0 # e0 :
66 t0 == a source word not containing a null. */
69 stq_u t0, 0(a0) # e0 :
71 ldq_u t0, 0(a1) # e0 :
74 cmpbge zero, t0, t
[all...]
H A Dev67-strchr.S32 ldq_u t0, 0(a0) # L : load first quadword Latency=3
49 cmpbge zero, t0, t2 # E : bits set iff byte == zero
54 xor t0, a1, t1 # E : make bytes == c zero
56 or t2, t3, t0 # E : bits set iff char match or zero match
58 andnot t0, t4, t0 # E : clear garbage bits
59 cttz t0, a2 # U0 : speculative (in case we get a match)
61 bne t0, $found # U :
69 $loop: ldq t0, 8(v0) # L : Latency=3
71 xor t0, a
[all...]
H A Dev67-strrchr.S38 ldq_u t0, 0(a0) # L : load first quadword Latency=3
55 cmpbge zero, t0, t1 # E : bits set iff byte == zero
57 xor t0, a1, t2 # E : make bytes == c zero
67 ldq t0, 8(v0) # L : load next quadword
75 xor t0, a1, t2 # E :
77 cmpbge zero, t0, t1 # E : bits set iff byte == zero
/linux-master/arch/csky/abiv2/
H A Dstrcmp.S18 ldw t0, (a3, 0)
21 cmpne t0, t1
24 tstnbz t0
28 ldw t0, (a3, 4)
30 cmpne t0, t1
32 tstnbz t0
35 ldw t0, (a3, 8)
37 cmpne t0, t1
39 tstnbz t0
42 ldw t0, (a
[all...]
H A Dstrcpy.S10 andi t0, a1, 3
11 bnez t0, 11f
87 xtrb0 t0, a2
88 st.b t0, (a3)
89 bez t0, 10f
90 xtrb1 t0, a2
91 st.b t0, (a3, 1)
92 bez t0, 10f
93 xtrb2 t0, a2
94 st.b t0, (a
[all...]
/linux-master/arch/mips/alchemy/common/
H A Dsleeper.S56 lw t0, 0(t1)
57 jalr t0
93 la t0, 1f
95 cache 0x14, 0(t0)
96 cache 0x14, 32(t0)
97 cache 0x14, 64(t0)
98 cache 0x14, 96(t0)
119 la t0, 1f
121 cache 0x14, 0(t0)
122 cache 0x14, 32(t0)
[all...]
/linux-master/arch/mips/fw/lib/
H A Dcall_o32.S73 PTR_LA t0,O32_FRAMESZ(sp)
77 lw t3,(t0)
78 REG_ADDU t0,SZREG
/linux-master/arch/mips/include/asm/mach-ath79/
H A Dkernel-entry-init.h17 mfc0 t0, CP0_CONFIG
19 and t0, t1 variable
20 ori t0, CONF_CM_CACHABLE_NONCOHERENT variable
21 mtc0 t0, CP0_CONFIG variable
/linux-master/arch/mips/include/asm/mach-malta/
H A Dkernel-entry-init.h35 * The following code uses the t0, t1, t2 and ra registers without
52 li t0, ((MIPS_SEGCFG_MK << MIPS_SEGCFG_AM_SHIFT) | \ variable
58 or t0, t2 variable
59 mtc0 t0, CP0_SEGCTL0 variable
62 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ variable
69 ins t0, t1, 16, 3 variable
70 mtc0 t0, CP0_SEGCTL1 variable
73 li t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) | \ variable
79 or t0, t2 variable
80 mtc0 t0, CP0_SEGCTL variable
83 mfc0 t0, $16, 5 variable
85 or t0, t0, t2 variable
86 mtc0 t0, $16, 5 variable
101 mfc0 t0, CP0_CONFIG, 1 variable
102 bgez t0, 9f variable
103 mfc0 t0, CP0_CONFIG, 2 variable
104 bgez t0, 9f variable
105 mfc0 t0, CP0_CONFIG, 3 variable
106 sll t0, t0, 6 /* SC bit */ variable
107 bgez t0, 9f variable
[all...]
/linux-master/arch/mips/include/asm/
H A Dpm.h112 LONG_L t0, 0(t1)
113 jalr t0
/linux-master/arch/mips/kernel/
H A Dbmips_5xxx_init.S33 and t0, kva, t2 ; \
36 9: cache op, 0(t0) ; \
37 bne t0, t1, 9b ; \
38 addu t0, linesize ; \
113 * Trashes: v0, v1, a0, t0
123 move t0, a0
150 move a0, t0
178 move a0, t0
208 * Trashes: v0, v1, a0, t0
216 move t0, a
[all...]
H A Dbmips_vec.S279 mfc0 t0, CP0_PRID
280 andi t2, t0, 0xff00
285 andi t0, 0xff
286 addiu t1, t0, -PRID_REV_BMIPS4380_HI
288 addiu t0, -PRID_REV_BMIPS4380_LO
289 bltz t0, 2f
291 mfc0 t0, $22, 3
294 or t0, t1
295 xor t0, t1
296 or t0, t
[all...]
H A Dr4k_switch.S47 PTR_ADDU t0, $28, _THREAD_SIZE - 32
48 set_saved_sp t0, t1, t2
/linux-master/arch/mips/kvm/
H A Dmsa.S151 lw t0, VCPU_MSA_CSR(a0)
154 * See kvm_mips_csr_die_notify() which handles t0 containing a value
158 _ctcmsa MSA_CSR, t0
/linux-master/arch/mips/power/
H A Dhibernate_asm.S15 PTR_LA t0, saved_regs
16 PTR_S ra, PT_R31(t0)
17 PTR_S sp, PT_R29(t0)
18 PTR_S fp, PT_R30(t0)
19 PTR_S gp, PT_R28(t0)
20 PTR_S s0, PT_R16(t0)
21 PTR_S s1, PT_R17(t0)
22 PTR_S s2, PT_R18(t0)
23 PTR_S s3, PT_R19(t0)
24 PTR_S s4, PT_R20(t0)
[all...]
/linux-master/arch/powerpc/crypto/
H A Daes-spe-modes.S125 #define ENDIAN_SWAP(t0, t1, s0, s1) \
126 rotrwi t0,s0,8; /* swap endianness for 2 GPRs */ \
128 rlwimi t0,s0,8,8,15; \
130 rlwimi t0,s0,8,24,31; \
133 #define GF128_MUL(d0, d1, d2, d3, t0) \
134 li t0,0x87; /* multiplication in GF128 */ \
136 iselgt t0,0,t0; \
144 xor d0,d0,t0;
/linux-master/arch/sparc/mm/
H A Dtsunami.S87 #define MIRROR_BLOCK(dst, src, offset, t0, t1, t2, t3) \
88 ldd [src + offset + 0x18], t0; \
89 std t0, [dst + offset + 0x18]; \
92 ldd [src + offset + 0x08], t0; \
93 std t0, [dst + offset + 0x08]; \
/linux-master/drivers/gpu/drm/gma500/
H A Dpsb_intel_sdvo_regs.h542 u8 t0; member in struct:psb_sdvo_panel_power_sequencing
/linux-master/drivers/soc/bcm/brcmstb/pm/
H A Ds2-mips.S42 move t0, a0
44 lw s0, 0(t0)
45 lw s1, 4(t0)
46 lw s2, 8(t0)
47 lw s3, 12(t0)
48 lw s4, 16(t0)
49 lw s5, 20(t0)
55 la t0, brcm_pm_do_s2
56 and t0, t1
61 1: cache 0x1c, 0(t0)
[all...]
H A Ds3-mips.S25 la t0, gp_regs
26 sw ra, 0(t0)
27 sw s0, 4(t0)
28 sw s1, 8(t0)
29 sw s2, 12(t0)
30 sw s3, 16(t0)
31 sw s4, 20(t0)
32 sw s5, 24(t0)
33 sw s6, 28(t0)
34 sw s7, 32(t0)
[all...]

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