Searched refs:s5 (Results 1 - 25 of 56) sorted by last modified time

123

/linux-master/arch/riscv/net/
H A Dbpf_jit_comp64.c48 [RV_REG_S5] = offsetof(struct pt_regs, s5),
/linux-master/arch/riscv/kernel/
H A Dprocess.c83 pr_cont(" s5 : " REG_FMT " s6 : " REG_FMT " s7 : " REG_FMT "\n",
84 regs->s5, regs->s6, regs->s7);
H A Dptrace.c224 REG_OFFSET_NAME(s5),
H A Dentry.S66 csrr s5, CSR_SCRATCH
72 REG_S s5, PT_TP(sp)
84 scs_load_current_if_task_changed s5
214 csrr s5, CSR_SCRATCH
220 REG_S s5, PT_TP(sp)
298 REG_S s5, TASK_THREAD_S5_RA(a3)
315 REG_L s5, TASK_THREAD_S5_RA(a4)
H A Dhead.S374 li s5, 0
H A Dsuspend_entry.S37 REG_S s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
/linux-master/arch/riscv/include/asm/
H A Dcompat.h61 compat_ulong_t s5; member in struct:compat_user_regs_struct
98 cregs->s5 = (compat_ulong_t) regs->s5;
135 regs->s5 = (unsigned long) cregs->s5;
H A Dkvm_host.h137 unsigned long s5; member in struct:kvm_cpu_context
/linux-master/arch/riscv/crypto/
H A Dchacha-riscv64-zvkb.S68 #define KEY5 s5
149 sd s5, 40(sp)
285 ld s5, 40(sp)
/linux-master/arch/loongarch/kernel/
H A Drelocate_kernel.S65 li.w s5, (1 << _PAGE_SHIFT) / SZREG
73 LONG_ADDI s5, s5, -1
74 beqz s5, process_entry
H A Drethook_trampoline.S34 cfi_st s5, PT_R28
69 cfi_ld s5, PT_R28
H A Dmcount_dyn.S57 PTR_S s5, sp, PT_R28
/linux-master/arch/loongarch/include/asm/
H A Dstackframe.h78 cfi_st s5, PT_R28, \docfi variable
193 cfi_ld s5, PT_R28, \docfi variable
H A Dasmmacro.h19 stptr.d s5, \thread, THREAD_REG28
33 ldptr.d s5, \thread, THREAD_REG28
/linux-master/tools/testing/selftests/kvm/riscv/
H A Dget-reg-list.c687 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5),
/linux-master/tools/testing/selftests/kvm/lib/riscv/
H A Dprocessor.c245 vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5);
276 core.regs.s4, core.regs.s5, core.regs.s6, core.regs.s7);
/linux-master/tools/testing/selftests/kvm/include/riscv/
H A Dprocessor.h74 unsigned long s5; member in struct:ex_regs
/linux-master/arch/mips/include/asm/
H A Dregdef.h137 #define s5 $21 macro
180 #define s5 $21 macro
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler_gfx10.asm595 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0]
622 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0]
H A Dcwsr_trap_handler_gfx9.asm470 s_movrels_b64 s4, s4 //s4 = s[4+m0], s5 = s[5+m0]
/linux-master/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_packet.c347 struct sparx5 *s5 = _sparx5; local
351 while (spx5_rd(s5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE) && poll-- > 0)
352 sparx5_xtr_grp(s5, XTR_QUEUE, false);
H A Dsparx5_main.c342 static int sparx5_init_ram(struct sparx5 *s5) argument
345 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
346 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
347 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
348 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
349 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
350 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
351 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
352 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
353 {spx5_reg_get(s5, VCAP_SUPER_RAM_INI
[all...]
/linux-master/arch/riscv/kvm/
H A Dvcpu_switch.S36 REG_S s5, (KVM_ARCH_HOST_S5)(a0)
96 REG_L s5, (KVM_ARCH_GUEST_S5)(a0)
140 REG_S s5, (KVM_ARCH_GUEST_S5)(a0)
201 REG_L s5, (KVM_ARCH_HOST_S5)(a0)
/linux-master/arch/mips/kernel/
H A Drelocate_kernel.S62 REG_L s5, (s2)
63 REG_S s5, (s4)
/linux-master/arch/arm64/crypto/
H A Dsm4-neon-core.S50 #define transpose_4x4_2x(s0, s1, s2, s3, s4, s5, s6, s7) \
55 zip1 RTMP4.4s, s4.4s, s5.4s; \
57 zip2 RTMP6.4s, s4.4s, s5.4s; \
64 zip2 s5.2d, RTMP4.2d, RTMP5.2d; \
78 #define rotate_clockwise_4x4_2x(s0, s1, s2, s3, s4, s5, s6, s7) \
83 zip1 RTMP4.4s, s5.4s, s4.4s; \
85 zip2 RTMP5.4s, s5.4s, s4.4s; \
92 zip2 s5.2d, RTMP6.2d, RTMP4.2d; \

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