Searched refs:r1 (Results 1 - 25 of 639) sorted by path

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/linux-master/arch/arc/include/asm/
H A Dunwind.h15 unsigned long r1; member in struct:arc700_regs
74 PTREGS_INFO(r1), \
/linux-master/arch/arc/include/uapi/asm/
H A Dptrace.h40 unsigned long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0; member in struct:user_regs_struct::__anon131
/linux-master/arch/arc/lib/
H A Dmemcmp.S17 or r12,r0,r1
22 ld r5,[r1,0]
39 ld_s r12,[r1,4]
42 ld.a r5,[r1,8]
54 ld r5,[r1,4]
61 sub_s r1,r0,1
62 bic_s r1,r1,r0
63 norm r1,r1
[all...]
H A Dmemcpy-700.S9 or r3,r0,r1
14 ld_s r12,[r1,0]
19 ld.a r12,[r1,4]
22 ld_s r3,[r1,4]
24 ld.a r12,[r1,8]
49 ldb_s r12,[r1,0]
53 ldb.a r12,[r1,1]
56 ldb_s r3,[r1,1]
58 ldb.a r12,[r1,2]
H A Dmemcpy-archs-unaligned.S29 LOADX (r6, r1)
30 LOADX (r8, r1)
31 LOADX (r10, r1)
32 LOADX (r4, r1)
42 ldb.ab r5, [r1, 1]
H A Dmemcpy-archs.S51 ldb.ab r5, [r1,1]
57 and.f r4, r1, 0x03
65 LOADX (r6, r1)
66 LOADX (r8, r1)
67 LOADX (r10, r1)
68 LOADX (r4, r1)
79 ldb.ab r5, [r1,1]
92 ldb.ab r5, [r1, 1]
97 ldh.ab r6, [r1, 2]
108 ld.ab r6, [r1,
[all...]
H A Dmemset.S14 extb_s r1,r1
15 asl r3,r1,8
17 or_s r1,r1,r3
20 stb r1,[r3,-1]
22 stw r1,[r3,-2]
26 stb.ab r1,[r4,1]
28 stw.ab r1,[r4,2]
31 asl r3,r1,1
[all...]
H A Dstrchr-700.S14 extb_s r1,r1
15 asl r5,r1,8
17 or r5,r5,r1
H A Dstrcmp-archs.S9 or r2, r0, r1
20 ld.ab r3, [r1, 4]
66 ldb.ab r3, [r1, 1]
H A Dstrcmp.S16 or r2,r0,r1
23 ld.ab r3,[r1,4]
32 sub_s r1,r0,1
33 bic_s r0,r0,r1 ; mask for least significant difference bit
34 sub r1,r5,r0
35 xor r0,r5,r1 ; mask for least significant difference byte
49 sub_s r1,r0,1
50 bic_s r0,r0,r1 ; mask for least significant difference bit
51 sub r1,r5,r0
52 xor r0,r5,r1 ; mas
[all...]
H A Dstrcpy-700.S19 or r2,r0,r1
23 ld_s r3,[r1,0]
25 bbit0.d r1,2,loop_start
34 ld.a r3,[r1,4]
37 ld.a r4,[r1,4]
49 r3z: bmsk.f r1,r3,7
52 r3z: lsr.f r1,r3,24
56 stb.ab r1,[r10,1]
61 ldb.ab r3,[r1,1]
H A Dstrlen.S15 asl_s r1,r0,3
17 asl r7,r4,r1
19 sub r1,r2,r7
20 bic_s r1,r1,r2
24 or.eq r12,r12,r1
30 mov_s r1,31
31 sub3 r7,r1,r0
32 sub r1,r2,r4
33 bic_s r1,r
[all...]
/linux-master/arch/arm/boot/compressed/
H A Dhead-sharpsl.S29 mov r1, #0x10000000 @ Base address of TC6393 chip
31 ldrh r3, [r1, #8] @ Load TC6393XB Revison: This is 0x0003
43 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
46 str r6, [r1, #0x280] @ to SCRATCH_UMSK
52 str r6, [r1, #0x280] @ to SCRATCH_UMSK
54 ldr r6, [r1, #0] @ Load Chip ID
84 ldr r1, .SCOOP2ADDR
87 strh r6, [r1]
88 ldrh r6, [r1]
126 * Corrupts: r1
[all...]
H A Dll_char_wr.S29 * r1 = char
40 mov r1, r1, lsl #3
57 orr r1, r1, #7
58 ldrb r7, [r6, r1]
67 sub r1, r1, #1 @ avoid using r7 directly after
69 ldrb r7, [r6, r1]
72 tst r1, #
[all...]
/linux-master/arch/arm/common/
H A Dsecure_cntvoff.S21 mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
22 orr r0, r1, #1
28 mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
/linux-master/arch/arm/crypto/
H A Dsha1-armv7-neon.S42 #define RDATA r1
295 * r1: data (64*nblks bytes)
/linux-master/arch/arm/kernel/
H A Dfiqasm.S27 mrs r1, cpsr
33 msr cpsr_c, r1 @ return to SVC mode
40 mrs r1, cpsr
46 msr cpsr_c, r1 @ return to SVC mode
/linux-master/arch/arm/lib/
H A Dashldi3.S33 #define al r1
37 #define ah r1
H A Dashrdi3.S33 #define al r1
37 #define ah r1
H A Dbswapsdi2.S13 rev r0, r1
14 mov r1, r3
27 mov ip, r1
29 eor r1, r0, r0, ror #16
30 mov r1, r1, lsr #8
33 bic r1, r1, #0xff00
34 eor r1, r1, r
[all...]
H A Dclear_user.S22 UNWIND(.save {r1, lr})
23 stmfd sp!, {r1, lr}
25 cmp r1, #4
34 sub r1, r1, ip @ 7 6 5 4 3 2 1
35 1: subs r1, r1, #8 @ -1 -2 -3 -4 -5 -6 -7
38 adds r1, r1, #4 @ 3 2 1 0 -1 -2 -3
40 2: tst r1, #
[all...]
H A Dcopy_page.S26 PLD( pld [r1, #0] )
27 PLD( pld [r1, #L1_CACHE_BYTES] )
29 ldmia r1!, {r3, r4, ip, lr} @ 4+1
30 1: PLD( pld [r1, #2 * L1_CACHE_BYTES])
31 PLD( pld [r1, #3 * L1_CACHE_BYTES])
35 ldmia r1!, {r3, r4, ip, lr} @ 4
39 ldmiagt r1!, {r3, r4, ip, lr} @ 4
41 PLD( ldmiaeq r1!, {r3, r4, ip, lr} )
H A Dcsumipv6.S15 ldmia r1, {r1 - r3, lr}
16 adcs ip, ip, r1
22 adcs r0, r0, r1
H A Dcsumpartial.S14 * Params : r0 = buffer, r1 = len, r2 = checksum
19 len .req r1
H A Ddiv64.S18 #define xl r1
23 #define xh r1

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