Searched refs:ioaddr (Results 1 - 25 of 305) sorted by path

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/linux-master/arch/m68k/coldfire/
H A Dnettel.c101 static void __init nettel_smc91x_setmac(unsigned int ioaddr, unsigned int flashaddr) argument
110 writew(macp[0], ioaddr + SMC91xx_BASEMAC);
111 writew(macp[1], ioaddr + SMC91xx_BASEMAC + 2);
112 writew(macp[2], ioaddr + SMC91xx_BASEMAC + 4);
/linux-master/drivers/atm/
H A Deni.h76 void __iomem *ioaddr; member in struct:eni_dev
/linux-master/drivers/i2c/busses/
H A Di2c-iop3xx.h90 void __iomem *ioaddr; member in struct:i2c_algo_iop3xx_data
/linux-master/drivers/mmc/host/
H A Dtoshsd.h171 void __iomem *ioaddr; /* mapped address */ member in struct:toshsd_host
/linux-master/drivers/net/arcnet/
H A Dcom20020.h122 int ioaddr, int val)
126 arcnet_outb(lp->config, ioaddr, COM20020_REG_W_CONFIG);
128 arcnet_outb(val, ioaddr, COM20020_REG_W_SUBADR);
121 com20020_set_subaddress(struct arcnet_local *lp, int ioaddr, int val) argument
/linux-master/drivers/net/ethernet/altera/
H A Daltera_utils.c9 void tse_set_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument
11 u32 value = csrrd32(ioaddr, offs);
13 csrwr32(value, ioaddr, offs);
16 void tse_clear_bit(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument
18 u32 value = csrrd32(ioaddr, offs);
20 csrwr32(value, ioaddr, offs);
23 int tse_bit_is_set(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument
25 u32 value = csrrd32(ioaddr, offs);
29 int tse_bit_is_clear(void __iomem *ioaddr, size_t offs, u32 bit_mask) argument
31 u32 value = csrrd32(ioaddr, off
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/linux-master/drivers/net/ethernet/dec/tulip/
H A D21142.c33 void __iomem *ioaddr = tp->base_addr; local
34 int csr12 = ioread32(ioaddr + CSR12);
37 int csr14 = ioread32(ioaddr + CSR14);
79 iowrite32(0, ioaddr + CSR13);
80 iowrite32(0x0003FFFF, ioaddr + CSR14);
81 iowrite16(t21142_csr15[dev->if_port], ioaddr + CSR15);
82 iowrite32(t21142_csr13[dev->if_port], ioaddr + CSR13);
87 iowrite32(0, ioaddr + CSR13);
88 iowrite32(0x0003FFFF, ioaddr + CSR14);
89 iowrite16(8, ioaddr
114 void __iomem *ioaddr = tp->base_addr; local
142 void __iomem *ioaddr = tp->base_addr; local
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H A Dtimer.c22 void __iomem *ioaddr = tp->base_addr; local
23 u32 csr12 = ioread32(ioaddr + CSR12);
30 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR6),
31 csr12, ioread32(ioaddr + CSR13),
32 ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
49 ioread32(ioaddr + CSR6),
128 tulip_tx_timeout_complete(tp, ioaddr);
144 void __iomem *ioaddr local
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/linux-master/drivers/net/ethernet/dlink/
H A Ddl2k.h373 void __iomem *ioaddr; member in struct:netdev_private
/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_dma.c21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) argument
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG);
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num));
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num));
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num));
62 writel(reg_val, ioaddr
96 sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) argument
105 sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) argument
112 sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) argument
118 sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) argument
131 sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) argument
140 sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) argument
149 sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) argument
161 sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) argument
174 sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) argument
186 sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) argument
258 sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, struct sxgbe_extra_stats *x) argument
325 sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) argument
335 sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) argument
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H A Dsxgbe_dma.h22 int (*init)(void __iomem *ioaddr, int fix_burst, int burst_map);
23 void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst,
26 void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum);
27 void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum);
28 void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum);
29 void (*start_tx)(void __iomem *ioaddr, int tchannels);
30 void (*start_tx_queue)(void __iomem *ioaddr, int dma_cnum);
31 void (*stop_tx)(void __iomem *ioaddr, int tchannels);
32 void (*stop_tx_queue)(void __iomem *ioaddr, int dma_cnum);
33 void (*start_rx)(void __iomem *ioaddr, in
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H A Dsxgbe_mtl.c20 static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg, argument
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) argument
56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG);
57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG);
58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG);
61 static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num, argument
68 reg_val = readl(ioaddr
73 sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num, int queue_fifo) argument
85 sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num) argument
94 sxgbe_mtl_disable_txqueue(void __iomem *ioaddr, int queue_num) argument
103 sxgbe_mtl_fc_active(void __iomem *ioaddr, int queue_num, int threshold) argument
115 sxgbe_mtl_fc_enable(void __iomem *ioaddr, int queue_num) argument
124 sxgbe_mtl_fc_deactive(void __iomem *ioaddr, int queue_num, int threshold) argument
136 sxgbe_mtl_fep_enable(void __iomem *ioaddr, int queue_num) argument
146 sxgbe_mtl_fep_disable(void __iomem *ioaddr, int queue_num) argument
156 sxgbe_mtl_fup_enable(void __iomem *ioaddr, int queue_num) argument
166 sxgbe_mtl_fup_disable(void __iomem *ioaddr, int queue_num) argument
177 sxgbe_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num, int tx_mode) argument
208 sxgbe_set_rx_mtl_mode(void __iomem *ioaddr, int queue_num, int rx_mode) argument
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H A Dsxgbe_mtl.h61 void (*mtl_init)(void __iomem *ioaddr, unsigned int etsalg,
64 void (*mtl_set_txfifosize)(void __iomem *ioaddr, int queue_num,
67 void (*mtl_set_rxfifosize)(void __iomem *ioaddr, int queue_num,
70 void (*mtl_enable_txqueue)(void __iomem *ioaddr, int queue_num);
72 void (*mtl_disable_txqueue)(void __iomem *ioaddr, int queue_num);
74 void (*set_tx_mtl_mode)(void __iomem *ioaddr, int queue_num,
77 void (*set_rx_mtl_mode)(void __iomem *ioaddr, int queue_num,
80 void (*mtl_dynamic_dma_rxqueue)(void __iomem *ioaddr);
82 void (*mtl_fc_active)(void __iomem *ioaddr, int queue_num,
85 void (*mtl_fc_deactive)(void __iomem *ioaddr, in
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/linux-master/drivers/net/ethernet/smsc/
H A Dsmc9194.h204 #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); }
207 #define SMC_DELAY() { inw( ioaddr + RCR );\
208 inw( ioaddr + RCR );\
209 inw( ioaddr + RCR ); }
215 mask = inb( ioaddr + INT_MASK );\
217 outb( mask, ioaddr + INT_MASK ); \
225 mask = inb( ioaddr + INT_MASK );\
227 outb( mask, ioaddr + INT_MASK ); \
/linux-master/drivers/net/wireless/intel/ipw2x00/
H A Dipw2100.h468 void __iomem *ioaddr; member in struct:ipw2100_priv
/linux-master/drivers/pcmcia/
H A Di82365.c148 unsigned int ioaddr; member in struct:i82365_socket
222 unsigned int port = socket[sock].ioaddr;
236 unsigned int port = socket[sock].ioaddr;
578 socket[sockets].ioaddr = port;
664 socket[sockets].ioaddr = port;
683 t->ioaddr, t->psock*0x40);
1302 release_region(socket[i].ioaddr, 2);
1333 release_region(socket[i].ioaddr, 2);
/linux-master/drivers/scsi/sym53c8xx_2/
H A Dsym_glue.h172 void __iomem * ioaddr; /* MMIO kernel io address */ member in struct:sym_shcb
196 void __iomem *ioaddr; member in struct:sym_device::__anon1096
H A Dsym_hipd.h184 #define INB_OFF(np, o) ioread8(np->s.ioaddr + (o))
185 #define INW_OFF(np, o) ioread16(np->s.ioaddr + (o))
186 #define INL_OFF(np, o) ioread32(np->s.ioaddr + (o))
188 #define OUTB_OFF(np, o, val) iowrite8((val), np->s.ioaddr + (o))
189 #define OUTW_OFF(np, o, val) iowrite16((val), np->s.ioaddr + (o))
190 #define OUTL_OFF(np, o, val) iowrite32((val), np->s.ioaddr + (o))
/linux-master/drivers/video/fbdev/savage/
H A Dsavagefb-i2c.c50 r = readl(chan->ioaddr + chan->reg);
55 writel(r, chan->ioaddr + chan->reg);
56 readl(chan->ioaddr + chan->reg); /* flush posted write */
64 r = readl(chan->ioaddr + chan->reg);
69 writel(r, chan->ioaddr + chan->reg);
70 readl(chan->ioaddr + chan->reg); /* flush posted write */
77 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SCL_IN));
84 return (0 != (readl(chan->ioaddr + chan->reg) & SAVAGE4_I2C_SDA_IN));
177 par->chan.ioaddr = par->mmio.vbase;
187 par->chan.ioaddr
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/linux-master/include/linux/rtc/
H A Dm48t59.h55 /* ioaddr mapped externally */
56 void __iomem *ioaddr; member in struct:m48t59_plat_data
/linux-master/include/linux/
H A Dscx200_gpio.h12 #define __SCx200_GPIO_IOADDR unsigned short ioaddr = scx200_gpio_base+0x10*bank
16 #define __SCx200_GPIO_OUT __asm__ __volatile__("outsl":"=mS" (shadow):"d" (ioaddr), "0" (shadow))
25 return (inl(ioaddr) & (1<<index)) ? 1 : 0;
/linux-master/arch/arm/mach-socfpga/
H A Docram.c65 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) argument
67 u32 value = readl(ioaddr);
70 writel(value, ioaddr);
73 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) argument
75 u32 value = readl(ioaddr);
78 writel(value, ioaddr);
81 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) argument
83 u32 value = readl(ioaddr);
92 static int altr_init_memory_port(void __iomem *ioaddr) argument
96 ecc_set_bits(ALTR_A10_ECC_INITA, (ioaddr
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/linux-master/arch/arm64/kvm/vgic/
H A Dvgic-kvm-device.c17 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr, argument
21 if (!IS_VGIC_ADDR_UNDEF(ioaddr))
H A Dvgic.h194 int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
/linux-master/arch/m68k/include/asm/
H A Dio_mm.h48 #define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
49 #define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
59 #define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
60 #define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
75 #define ENEC_ISA_IO_B(ioaddr) (enec_isa_read_bas
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