/linux-master/arch/alpha/include/asm/ |
H A D | core_irongate.h | 106 igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */ member in struct:__anon6
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/linux-master/arch/alpha/kernel/ |
H A D | head.S | 61 # on the PC164 (at least), since that PALcode manages the interrupt
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H A D | smc37c93x.c | 134 unsigned long interrupt) 152 outb(interrupt, dataPort); 169 outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */ 172 outb(INTERRUPT_SEL_2, indexPort); /* Secondary interrupt select */ 198 outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */ 131 SMCEnableDevice(unsigned long baseAddr, unsigned long device, unsigned long portaddr, unsigned long interrupt) argument
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/linux-master/arch/arm/kernel/ |
H A D | smp_twd.c | 18 #include <linux/interrupt.h> 77 * local_timer_ack: checks for a local timer interrupt. 79 * If a local timer interrupt has occurred, acknowledge and return 1. 162 /* enable, no interrupt or reload */ 284 pr_err("twd: can't register interrupt %d (%d)\n", twd_ppi, err);
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/linux-master/arch/arm/mach-ep93xx/ |
H A D | dma.c | 20 #include <linux/interrupt.h>
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/linux-master/arch/arm/mach-omap2/ |
H A D | sleep24xx.S | 63 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
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/linux-master/arch/arm/mach-pxa/ |
H A D | am200epd.c | 26 #include <linux/interrupt.h>
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/linux-master/arch/arm/mach-rpc/ |
H A D | dma.c | 11 #include <linux/interrupt.h>
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/linux-master/arch/arm/mach-sa1100/ |
H A D | ssp.c | 14 #include <linux/interrupt.h>
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/linux-master/arch/arm64/boot/dts/sprd/ |
H A D | sharkl64.dtsi | 10 interrupt-parent = <&gic>;
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/linux-master/arch/hexagon/kernel/ |
H A D | asm-offsets.c | 15 #include <linux/interrupt.h>
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H A D | irq_cpu.c | 3 * First-level interrupt controller model for Hexagon. 8 #include <linux/interrupt.h> 54 * The hexagon core comes with a first-level interrupt controller 57 * macro cells that provide one or more second-level interrupt 63 * The first-level interrupt controller is wrapped by the VM, which 64 * virtualizes the interrupt controller for us. It provides a very
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/linux-master/arch/m68k/amiga/ |
H A D | amiints.c | 2 * Amiga Linux interrupt handling code 10 #include <linux/interrupt.h> 22 * Enable/disable a particular machine specific interrupt source. 23 * Note that this may affect other interrupts in case of a shared interrupt. 25 * internal data, that may not be changed by the interrupt at the same time. 46 * The builtin Amiga hardware interrupt handlers. 53 /* if serial transmit buffer empty, interrupt */ 59 /* if floppy disk transfer complete, interrupt */ 65 /* if software interrupt set, interrupt */ [all...] |
H A D | cia.c | 20 #include <linux/interrupt.h> 48 * Cause or clear CIA interrupts, return old interrupt status. 66 * Enable or disable CIA interrupts, return old interrupt mask, 94 * the timer interrupt serviced. 145 * for external interrupts, we link the CIA interrupt sources 184 /* clear any pending interrupt and turn off all interrupts */ 194 pr_err("Couldn't register %s interrupt\n", base->name);
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/linux-master/arch/m68k/coldfire/ |
H A D | amcore.c | 15 #include <linux/interrupt.h> 50 /* IRQ line the device's interrupt pin is connected to */ 75 /* Set the dm9000 interrupt to be auto-vectored */
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H A D | intc-5249.c | 14 #include <linux/interrupt.h> 52 /* GPIO interrupt sources */
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H A D | intc-525x.c | 15 #include <linux/interrupt.h> 79 /* set the interrupt base for the second interrupt controller */ 82 /* GPIO interrupt sources */
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H A D | intc-5272.c | 2 * intc.c -- interrupt controller or ColdFire 5272 SoC 14 #include <linux/interrupt.h> 23 * The 5272 ColdFire interrupt controller is nothing like any other 24 * ColdFire interrupt controller - it truly is completely different. 35 * internal interrupt sources which are level triggered). Which means 77 * The act of masking the interrupt also has a side effect of 'ack'ing 78 * an interrupt on this irq (for the external irqs). So this mask function 144 * of masking an interrupt. 165 /* Mask all interrupt sources */
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/linux-master/arch/m68k/include/asm/ |
H A D | atari_stdma.h | 7 #include <linux/interrupt.h>
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H A D | sun3ints.h | 2 * sun3ints.h -- Linux/Sun3 interrupt handling code definitions 15 #include <linux/interrupt.h>
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/linux-master/arch/m68k/kernel/ |
H A D | irq.c | 15 #include <linux/interrupt.h>
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/linux-master/arch/mips/alchemy/common/ |
H A D | dma.c | 38 #include <linux/interrupt.h> 55 * done interrupt, you won't know the irq number until the DMA channel is
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H A D | irq.c | 30 #include <linux/interrupt.h> 80 /* NOTE on interrupt priorities: The original writers of this code said: 83 * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT) 717 /* initialize interrupt controller to a safe state */ 783 /* save 4 interrupt mask status registers */ 931 /* disable & ack all possible interrupt sources */
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/linux-master/arch/mips/alchemy/devboards/ |
H A D | bcsr.c | 11 #include <linux/interrupt.h>
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/linux-master/arch/mips/bcm47xx/ |
H A D | irq.c | 28 #include <linux/interrupt.h>
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