| /linux-master/arch/arm/include/asm/ |
| H A D | barrier.h | 21 #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") macro
33 #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ macro
40 #define dmb(x) __asm__ __volatile__ ("" : : : "memory") macro
45 #define dmb(x) __asm__ __volatile__ ("" : : : "memory") macro
67 #define dma_rmb() dmb(osh)
68 #define dma_wmb() dmb(oshst)
77 #define __smp_mb() dmb(ish)
79 #define __smp_wmb() dmb(ishst)
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| H A D | assembler.h | 380 ALT_SMP(dmb ish)
382 ALT_SMP(W(dmb) ish)
385 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
403 dmb ish
405 W(dmb) ish
408 mcr p15, 0, r0, c7, c10, 5 @ dmb
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| /linux-master/arch/arm/kernel/ |
| H A D | smp_tlb.c | 153 dmb();
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| /linux-master/arch/arm/mach-socfpga/ |
| H A D | self-refresh.S | 85 dmb
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| /linux-master/arch/arm/common/ |
| H A D | mcpm_entry.c | 49 dmb();
65 dmb();
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| H A D | mcpm_head.S | 123 dmb
138 dmb
150 dmb
154 dmb
175 dmb
184 dmb
198 dmb
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| H A D | vlock.S | 31 dmb
35 dmb
82 dmb
95 dmb
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| /linux-master/arch/arm/crypto/ |
| H A D | sha512-armv4.pl | 601 dmb @ errata #451034 on early Cortex A8
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| /linux-master/arch/arm/mach-bcm/ |
| H A D | platsmp-brcmstb.c | 67 dmb();
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| /linux-master/arch/arm/mach-omap2/ |
| H A D | omap-smc.S | 52 dmb
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| H A D | sleep33xx.S | 133 dmb
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| H A D | sleep34xx.S | 97 dmb @ data memory barrier
213 dmb
418 dmb @ data memory barrier
429 dmb @ data memory barrier
444 dmb @ data memory barrier
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| H A D | sleep43xx.S | 263 dmb
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| H A D | sleep44xx.S | 350 dmb
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| /linux-master/arch/arm/mach-tegra/ |
| H A D | sleep.S | 37 dmb @ ensure ordering
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| /linux-master/arch/arm/mm/ |
| H A D | cache-b15-rac.c | 66 dmb();
76 /* This dmb() is required to force the Bus Interface Unit
80 dmb();
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| H A D | cache-v7.S | 99 dmb @ ensure ordering with previous memory accesses
127 dmb @ ensure ordering with previous memory accesses
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| H A D | cache-v7m.S | 175 dmb @ ensure ordering with previous memory accesses
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| /linux-master/arch/arm64/include/asm/ |
| H A D | atomic_ll_sc.h | 86 ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
90 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
101 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
182 ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
186 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
197 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
230 " dmb ish\n"
290 __CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
291 __CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
292 __CMPXCHG_CASE(w, , mb_, 32, dmb is
[all...] |
| H A D | barrier.h | 28 #define dmb(opt) asm volatile("dmb " #opt : : : "memory") macro
60 #define __dma_mb() dmb(osh)
61 #define __dma_rmb() dmb(oshld)
62 #define __dma_wmb() dmb(oshst)
119 #define __smp_mb() dmb(ish)
120 #define __smp_rmb() dmb(ishld)
121 #define __smp_wmb() dmb(ishst)
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| H A D | cmpxchg.h | 18 * barrier case is generated as release+dmb for the former and
57 __XCHG_CASE(w, b, mb_, 8, dmb ish, nop, , a, l, "memory")
58 __XCHG_CASE(w, h, mb_, 16, dmb ish, nop, , a, l, "memory")
59 __XCHG_CASE(w, , mb_, 32, dmb ish, nop, , a, l, "memory")
60 __XCHG_CASE( , , mb_, 64, dmb ish, nop, , a, l, "memory")
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| H A D | insn.h | 419 __AARCH64_INSN_FUNCS(dmb, 0xFFFFF0FF, 0xD50330BF)
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| /linux-master/arch/arm64/include/asm/vdso/ |
| H A D | compat_barrier.h | 17 #ifdef dmb
18 #undef dmb macro
21 #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") macro
23 #define aarch32_smp_mb() dmb(ish)
24 #define aarch32_smp_rmb() dmb(ishld)
25 #define aarch32_smp_wmb() dmb(ishst)
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| /linux-master/arch/arm64/kernel/ |
| H A D | armv8_deprecated.c | 272 * dmb - mcr p15, 0, Rt, c7, c10, 5
276 dmb(sy);
278 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
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| H A D | head.S | 101 dmb sy
177 dmb sy // needed before dc ivac with
454 dmb sy
|