Searched refs:channel (Results 1 - 25 of 1958) sorted by path

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/linux-master/Documentation/networking/
H A Dmac80211-auth-assoc-deauth.txt26 mac80211->driver: config(channel, channel type)
54 mac80211->driver: config(channel, channel type)
94 mac80211->driver: config(channel type to non-HT)
/linux-master/Documentation/networking/mac80211_hwsim/
H A Dhostapd.conf5 channel=1
/linux-master/arch/alpha/include/asm/
H A Dconsole.h14 extern long callback_read(long channel, long count, const char *buf, long lbn);
/linux-master/arch/m68k/include/asm/
H A Dmac_iop.h43 /* IOP channel states */
53 #define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
142 uint channel; /* channel number */ member in struct:iop_msg
/linux-master/arch/mips/include/asm/txx9/
H A Dtx4927pcic.h195 struct pci_controller *channel);
197 struct pci_controller *channel, int extarb);
/linux-master/arch/mips/kernel/
H A Drtlx.c38 struct rtlx_channel *chan = &rtlx->channel[i];
104 pr_debug("rtlx_open channel %d already opened\n", index);
165 chan = &rtlx->channel[index];
188 rtlx->channel[index].lx_state = RTLX_STATE_UNUSED;
199 chan = &rtlx->channel[index];
236 struct rtlx_channel *chan = &rtlx->channel[index];
251 lx = &rtlx->channel[index];
294 rt = &rtlx->channel[index];
/linux-master/arch/powerpc/boot/dts/fsl/
H A Delo3-dma-0.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
53 compatible = "fsl,eloplus-dma-channel";
57 dma-channel@180 {
58 compatible = "fsl,eloplus-dma-channel";
62 dma-channel@300 {
63 compatible = "fsl,eloplus-dma-channel";
[all...]
H A Delo3-dma-1.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
53 compatible = "fsl,eloplus-dma-channel";
57 dma-channel@180 {
58 compatible = "fsl,eloplus-dma-channel";
62 dma-channel@300 {
63 compatible = "fsl,eloplus-dma-channel";
[all...]
H A Delo3-dma-2.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
47 dma-channel@80 {
48 compatible = "fsl,eloplus-dma-channel";
52 dma-channel@100 {
53 compatible = "fsl,eloplus-dma-channel";
57 dma-channel@180 {
58 compatible = "fsl,eloplus-dma-channel";
62 dma-channel@300 {
63 compatible = "fsl,eloplus-dma-channel";
[all...]
H A Dpq3-dma-0.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
H A Dpq3-dma-1.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
H A Dpq3-sec2.1-0.dtsi40 fsl,channel-fifo-len = <24>;
H A Dpq3-sec3.0-0.dtsi42 fsl,channel-fifo-len = <24>;
H A Dpq3-sec3.1-0.dtsi42 fsl,channel-fifo-len = <24>;
H A Dpq3-sec3.3-0.dtsi42 fsl,channel-fifo-len = <24>;
H A Dqoriq-dma-0.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
H A Dqoriq-dma-1.dtsi42 dma-channel@0 {
43 compatible = "fsl,eloplus-dma-channel";
48 dma-channel@80 {
49 compatible = "fsl,eloplus-dma-channel";
54 dma-channel@100 {
55 compatible = "fsl,eloplus-dma-channel";
60 dma-channel@180 {
61 compatible = "fsl,eloplus-dma-channel";
/linux-master/arch/powerpc/platforms/maple/
H A Dmaple.h13 extern int maple_pci_get_legacy_ide_irq(struct pci_dev *dev, int channel);
/linux-master/arch/sh/boards/mach-hp6xx/
H A Dsetup.c69 sh_dac_enable(pdata->channel);
87 sh_dac_output(0, pdata->channel);
88 sh_dac_disable(pdata->channel);
93 .channel = 1,
/linux-master/arch/sh/drivers/dma/
H A Ddma-g2.c37 struct g2_channel channel[G2_NR_DMA_CHANNELS]; member in struct:g2_dma_info
48 ((g2_dma->channel[i].size - \
77 g2_dma->channel[chan_nr].chan_enable = 1;
78 g2_dma->channel[chan_nr].xfer_enable = 1;
87 g2_dma->channel[chan_nr].chan_enable = 0;
88 g2_dma->channel[chan_nr].xfer_enable = 0;
121 g2_dma->channel[chan_nr].g2_addr = chan->dar & 0x1fffffe0;
122 g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0;
123 g2_dma->channel[chan_nr].size = (chan->count & ~31) | 0x80000000;
124 g2_dma->channel[chan_n
[all...]
/linux-master/arch/sh/include/cpu-sh3/cpu/
H A Ddac.h18 static __inline__ void sh_dac_enable(int channel) argument
22 if(channel) v |= DACR_DAOE1;
27 static __inline__ void sh_dac_disable(int channel) argument
31 if(channel) v &= ~DACR_DAOE1;
36 static __inline__ void sh_dac_output(u8 value, int channel) argument
38 if(channel) __raw_writeb(value,DADR1);
/linux-master/arch/sh/kernel/cpu/
H A Dadc.c13 int adc_single(unsigned int channel) argument
18 if (channel >= 8) return -1;
20 off = (channel & 0x03) << 2;
23 csr = channel | ADCSR_ADST | ADCSR_CKS;
/linux-master/drivers/gpu/drm/sun4i/
H A Dsun8i_ui_scaler.c92 static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel) argument
99 DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
103 DE2_UI_SCALER_UNIT_SIZE * (channel - vi_num);
H A Dsun8i_vi_scaler.c836 static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel) argument
840 DE3_VI_SCALER_UNIT_SIZE * channel;
843 DE2_VI_SCALER_UNIT_SIZE * channel;
/linux-master/drivers/gpu/host1x/hw/
H A Dhw_host1x01_sync.h68 static inline u32 host1x_sync_cf_setup_r(unsigned int channel) argument
70 return 0x80 + channel * REGISTER_STRIDE;
72 #define HOST1X_SYNC_CF_SETUP(channel) \
73 host1x_sync_cf_setup_r(channel)
158 static inline u32 host1x_sync_cbread_r(unsigned int channel) argument
160 return 0x720 + channel * REGISTER_STRIDE;
162 #define HOST1X_SYNC_CBREAD(channel) \
163 host1x_sync_cbread_r(channel)
212 static inline u32 host1x_sync_cbstat_r(unsigned int channel) argument
214 return 0x758 + channel * REGISTER_STRID
[all...]

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