Searched refs:cache (Results 1 - 25 of 961) sorted by path

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/linux-master/arch/arc/mm/
H A DMakefile7 obj-y += tlb.o tlbex.o cache.o mmap.o
/linux-master/arch/arm/boot/compressed/
H A Dhead-xscale.S17 @ Data cache might be active.
18 @ Be sure to flush kernel binary out of the cache,
21 @ memory to be sure we hit the same cache.
/linux-master/arch/arm/include/asm/
H A Dglue-cache.h3 * arch/arm/include/asm/glue-cache.h
126 #error Unknown cache maintenance model
H A Dprocinfo.h39 struct cpu_cache_fns *cache; member in struct:proc_info_list
/linux-master/arch/arm/lib/
H A Dcopy_page.S12 #include <asm/cache.h>
/linux-master/arch/arm/mach-exynos/
H A Dsleep.S11 #include <asm/hardware/cache-l2x0.h>
/linux-master/arch/arm/mach-imx/
H A Dsystem.c21 #include <asm/hardware/cache-l2x0.h>
92 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
/linux-master/arch/arm/mach-npcm/
H A Dnpcm7xx.c10 #include <asm/hardware/cache-l2x0.h>
/linux-master/arch/arm/mach-sa1100/
H A Dsleep.S41 @ Pre-load __loop_udelay into the I-cache
46 @ The following must all exist in a single cache line to
/linux-master/arch/arm/mm/
H A Dcache-l2x0-pmu.c3 * L220/L310 cache controller support
16 #include <asm/hardware/cache-l2x0.h>
H A Dcache-v4.S3 * linux/arch/arm/mm/cache-v4.S
25 * Invalidate all cache entries in a particular address
35 * Clean and invalidate the entire cache.
40 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
49 * Invalidate a range of cache entries in the specified
59 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache
95 * Ensure no D cache aliasing occurs, either with itself or
96 * the I cache
115 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
H A Dcache-v4wt.S3 * linux/arch/arm/mm/cache-v4wt.S
7 * ARMv4 write through cache operations support.
18 * The size of one data cache line.
23 * The number of data cache segments.
28 * The number of lines in a cache segment.
34 * clean the whole cache, rather than using the individual
35 * cache line maintenance instructions.
48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
55 * Invalidate all cache entries in a particular address
63 * Clean and invalidate the entire cache
[all...]
H A Ddma.h5 #include <asm/glue-cache.h>
13 * Their sole purpose is to ensure that data held in the cache
24 * Their sole purpose is to ensure that data held in the cache
H A Dl2c-l2x0-resume.S4 * the settings of their L2 cache controller before restoring the
11 #include <asm/hardware/cache-l2x0.h>
35 @ and can be written whether or not the L2 cache is enabled
43 @ Don't setup the L2 cache if it is already enabled
/linux-master/arch/m68k/fpsp040/
H A Dsetox.S29 | (so the instructions and data are not in cache), and the
509 | MOVE.W #$3FA5,EXPA3 ...load EXPA3 in cache
521 | MOVE.W #0,2(%a1) ...load 2^(J/64) in cache
675 | MOVE.W #$3FC5,EM1A2 ...load EM1A2 in cache
688 | MOVE.W #0,2(%a1) ...load 2^(J/64) in cache
H A Dslog2.S25 | in cache), and the second one is measured when the
/linux-master/arch/m68k/mm/
H A DMakefile8 obj-$(CONFIG_MMU) += cache.o fault.o
/linux-master/arch/microblaze/kernel/cpu/
H A DMakefile13 obj-y += cache.o cpuinfo.o cpuinfo-pvr-full.o cpuinfo-static.o mb.o pvr.o
/linux-master/arch/mips/alchemy/common/
H A Dsleeper.S92 /* cache following instructions, as memory gets put to sleep */
95 cache 0x14, 0(t0)
96 cache 0x14, 32(t0)
97 cache 0x14, 64(t0)
98 cache 0x14, 96(t0)
118 /* cache following instructions, as memory gets put to sleep */
121 cache 0x14, 0(t0)
122 cache 0x14, 32(t0)
123 cache 0x14, 64(t0)
124 cache
[all...]
/linux-master/arch/mips/include/asm/fw/arc/
H A Dhinv.h105 unsigned short c_size; /* cache size in 4K pages */
107 unsigned short c_size; /* cache size in 4K pages */
111 } cache; member in union:key_u
/linux-master/arch/mips/kernel/
H A Dbmips_5xxx_init.S36 9: cache op, 0(t0) ; \
111 * Returns: v0 = i cache size, v1 = I cache line size
112 * Description: compute the I-cache size and I-cache line size
129 * the instruction cache:
145 * This field contains the line size of the instruction cache:
146 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
173 * This field contains the set associativity of the instruction cache.
185 * set associativiy, to get the cache siz
[all...]
H A Dbmips_vec.S190 /* initialize CPU1's local I-cache */
197 1: cache Index_Store_Tag_I, 0(k0)
/linux-master/arch/mips/mm/
H A Dcex-sb1.S18 * Based on SiByte sample software cache-err/cerr.S
94 * in the L2 cache or Memory Controller and cannot be
108 cache Index_Invalidate_I,(0<<13)(k0)
109 cache Index_Invalidate_I,(1<<13)(k0)
110 cache Index_Invalidate_I,(2<<13)(k0)
111 cache Index_Invalidate_I,(3<<13)(k0)
/linux-master/arch/nios2/boot/compressed/
H A Dhead.S18 #include <asm/cache.h>
24 /* invalidate all instruction cache */
30 /* invalidate all data cache */
51 /* flush the data cache after moving */
87 /* flush all data cache after decompressing */
93 /* flush all instruction cache */
/linux-master/arch/nios2/kernel/
H A Dhead.S21 #include <asm/cache.h>
67 /* Initialize all cache lines within the instruction cache */
115 * After the instruction cache is initialized, the data cache must
137 flushd 0(r2) /* Flush cache for safety */

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