/haiku/src/add-ons/accelerants/ati/ |
H A D | rage128.h | 283 return INREG(R128_CLOCK_CNTL_DATA);
|
H A D | rage128_overlay.cpp | 137 while (!(INREG(R128_OV0_REG_LOAD_CNTL) & (1 << 3)))
|
H A D | mach64_overlay.cpp | 68 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_EXT_REG_EN); // enable reg block 1
|
H A D | rage128_mode.cpp | 288 uint32 busCntl = INREG(R128_BUS_CNTL);
|
H A D | accelerant.h | 238 #define INREG(addr) *((vuint32*)(gInfo.regs + addr)) macro 247 (OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))
|
H A D | mach64.h | 497 return INREG(LCD_DATA);
|
H A D | mach64_dpms.cpp | 34 uint32 tmp = INREG(CRTC_GEN_CNTL);
|
H A D | mach64_draw.cpp | 25 uint32 genTestCntl = INREG(GEN_TEST_CNTL) & ~GUI_ENGINE_ENABLE; 31 OUTREG(BUS_CNTL, INREG(BUS_CNTL) | BUS_HOST_ERR_ACK | BUS_FIFO_ERR_ACK);
|
H A D | mach64_init.cpp | 56 uint32 memCntl = INREG(MEM_CNTL); 72 int memType = INREG(CONFIG_STAT0) & 0x7; 118 uint32 dspConfig = INREG(DSP_CONFIG); 182 uint32 memCntl = INREG(MEM_CNTL); 236 while ((INREG(FIFO_STAT) & 0xffff) > (0x8000ul >> entries)) ; 249 while (INREG(GUI_STAT) & ENGINE_BUSY) ;
|
H A D | mach64_mode.cpp | 108 uint32 crtc_gen_cntl = INREG(CRTC_GEN_CNTL); 258 uint32 crtc_gen_cntl = INREG(CRTC_GEN_CNTL) &
|
/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | vip.c | 48 INREG( regs, RADEON_VIPH_REG_DATA ); 62 *data = INREG( regs, RADEON_VIPH_REG_DATA ); 127 INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 134 INREG( regs, RADEON_VIPH_REG_DATA); 143 tmp = INREG( regs, RADEON_VIPH_TIMEOUT_STAT); 150 *buffer=(uint8)(INREG( regs, RADEON_VIPH_REG_DATA) & 0xff); 153 *(uint16 *)buffer=(uint16) (INREG( regs, RADEON_VIPH_REG_DATA) & 0xffff); 156 *(uint32 *)buffer=(uint32) ( INREG( regs, RADEON_VIPH_REG_DATA) & 0xffffffff); 166 (INREG( regs, RADEON_VIPH_TIMEOUT_STAT) & 0xffffff00) | RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS); 311 OUTREG( regs, RADEON_VIPH_TIMEOUT_STAT, (INREG( reg [all...] |
H A D | mem_controller.c | 42 uint32 aper0 = INREG( di->regs, RADEON_CONFIG_APER_0_BASE ); 119 tom = INREG( di->regs, RADEON_NB_TOM );
|
H A D | init.c | 313 di->dac2_cntl = INREG( di->regs, RADEON_DAC_CNTL2 ); 316 si->tmds_pll_cntl = INREG( di->regs, RADEON_TMDS_PLL_CNTL); 317 si->tmds_transmitter_cntl = INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL); 323 INREG( di->regs, RADEON_LVDS_GEN_CNTL )); 325 INREG( di->regs, RADEON_LVDS_PLL_CNTL )); 327 INREG( di->regs, RADEON_TMDS_PLL_CNTL )); 329 INREG( di->regs, RADEON_TMDS_TRANSMITTER_CNTL )); 331 INREG( di->regs, RADEON_FP_GEN_CNTL )); 333 INREG( di->regs, RADEON_FP2_GEN_CNTL )); 335 INREG( d [all...] |
H A D | bios.c | 214 tmp = INREG( di->regs, RADEON_BIOS_4_SCRATCH ); 252 tmp = INREG( di->regs, RADEON_FP_GEN_CNTL); 634 ((INREG( regs, RADEON_FP_VERT_STRETCH ) & RADEON_VERT_PANEL_SIZE) 638 (((INREG( regs, RADEON_FP_HORZ_STRETCH ) & RADEON_HORZ_PANEL_SIZE) 654 r = INREG( regs, RADEON_FP_CRTC_H_TOTAL_DISP ); 662 r = INREG( regs, RADEON_FP_H_SYNC_STRT_WID ); 674 r = INREG( regs, RADEON_FP_CRTC_V_TOTAL_DISP ); 681 r = INREG( regs, RADEON_FP_V_SYNC_STRT_WID ); 687 r = INREG( regs, RADEON_CRTC_H_TOTAL_DISP ); 694 r = INREG( reg [all...] |
H A D | PCI_GART.c | 297 INREG( regs, RADEON_CP_CSQ_CNTL );
|
H A D | CP_setup.c | 130 if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) { 147 INREG( di->regs, RADEON_RBBM_STATUS ), 148 INREG( di->regs, RADEON_CP_STAT ), 149 INREG( di->regs, RADEON_AIC_TLB_ADDR ), 150 INREG( di->regs, RADEON_AIC_TLB_DATA )); 167 int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK; 192 if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT ) 217 clock_cntl_index = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); 231 host_path_cntl = INREG( regs, RADEON_HOST_PATH_CNTL ); 232 rbbm_soft_reset = INREG( reg [all...] |
H A D | irq.c | 110 full_int_status = INREG(regs, RADEON_GEN_INT_STATUS); 111 int_status = full_int_status & INREG(regs, RADEON_GEN_INT_CNTL); 128 cap_status = INREG(regs, RADEON_CAP_INT_STATUS); 129 cap_status &= INREG(regs, RADEON_CAP_INT_CNTL);
|
H A D | DMA.c | 176 while( (INREG( di->regs, RADEON_DMA_VID_STATUS ) & RADEON_DMA_STATUS_ACTIVE) != 0 ) {
|
H A D | pll_access.c | 24 INREG( regs, RADEON_CLOCK_CNTL_DATA); 25 INREG( regs, RADEON_CRTC_GEN_CNTL); 50 save = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); 53 tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA ); 65 res = INREG( regs, RADEON_CLOCK_CNTL_DATA );
|
/haiku/src/add-ons/accelerants/radeon/ |
H A D | CP.c | 59 //space = INREG( ai->regs, RADEON_CP_RB_RPTR ) - cp->ring.tail; 89 //INREG( ai->regs, RADEON_SCRATCH_REG1 ); 339 INREG( ai->regs, RADEON_CP_RB_RPTR ); 350 //INREG( ai->regs, RADEON_CP_RB_RPTR );
|
H A D | Cursor.c | 227 tmp = INREG( ai->regs, RADEON_CRTC_GEN_CNTL ); 238 tmp = INREG( ai->regs, RADEON_CRTC2_GEN_CNTL );
|
H A D | monitor_detection.c | 43 value = INREG(regs, info->port); 59 value = INREG(regs, info->port); 109 old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNTL); 116 old_dac_ext_cntl = INREG(regs, RADEON_DAC_EXT_CNTL); 124 old_dac_cntl = INREG(regs, RADEON_DAC_CNTL); 137 found = (INREG(regs, RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) != 0; 185 old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL); 192 old_tv_dac_cntl = INREG(regs, RADEON_TV_DAC_CNTL); 204 old_dac_cntl2 = INREG(regs, RADEON_DAC_CNTL2); 214 found = (INREG(reg [all...] |
H A D | overlay.c | 852 while( (INREG( regs, RADEON_OV0_REG_LOAD_CNTL) 981 while( (INREG( regs, RADEON_OV0_REG_LOAD_CNTL)
|
/haiku/headers/private/graphics/radeon/ |
H A D | mmio.h | 18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr)))) macro 24 uint32 tmp = INREG( (regs), (addr) ); \
|
/haiku/src/add-ons/accelerants/3dfx/ |
H A D | accelerant.h | 188 (OUTREG(addr, (INREG(addr) & ~(mask)) | ((value) & (mask))))
|