Searched refs:CKSEG1ADDR (Results 1 - 25 of 42) sorted by path

12

/linux-master/arch/mips/cobalt/
H A Dpci.c38 .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE),
H A Dreset.c20 #define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
H A Dsetup.c81 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
115 setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0);
/linux-master/arch/mips/dec/
H A Decc-berr.c144 (void *)CKSEG1ADDR(address);
227 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
229 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
230 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
245 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
246 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
248 kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
249 kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
H A Dkn01-berr.c49 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
62 volatile u32 *kn01_erraddr = (void *)CKSEG1ADDR(KN01_SLOT_BASE +
150 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
177 volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
H A Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
H A Dkn02xa-berr.c29 volatile u32 *mer = (void *)CKSEG1ADDR(KN02XA_MER);
30 volatile u32 *mem_intr = (void *)CKSEG1ADDR(KN02XA_MEM_INTR);
40 volatile u32 *kn02xa_mer = (void *)CKSEG1ADDR(KN02XA_MER);
41 volatile u32 *kn02xa_ear = (void *)CKSEG1ADDR(KN02XA_EAR);
126 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
H A Dreset.c17 noret_func_t func = (void *)CKSEG1ADDR(0x1fc00000);
H A Dint-handler.S30 #define KN02_CSR_BASE CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR)
31 #define KN02XA_IOASIC_BASE CKSEG1ADDR(KN02XA_SLOT_BASE + IOASIC_IOCTL)
32 #define KN03_IOASIC_BASE CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_IOCTL)
/linux-master/arch/mips/dec/prom/
H A Didentify.c74 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
82 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN01_RTC);
91 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + KN02_RTC);
100 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
101 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
110 ioasic_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_IOCTL);
111 dec_rtc_base = (void *)CKSEG1ADDR(dec_kn_slot_base + IOASIC_TOY);
/linux-master/arch/mips/generic/
H A Dboard-sead3.c19 #define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
22 #define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
/linux-master/arch/mips/include/asm/mach-cobalt/
H A Dmach-gt64120.h12 #define GT64120_BASE CKSEG1ADDR(GT_DEF_BASE)
/linux-master/arch/mips/include/asm/
H A Dvga.h19 #define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
H A Daddrspace.h79 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro
86 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
H A Dbarrier.h56 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
/linux-master/arch/mips/pci/
H A Dops-bonito64.c19 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
H A Dpci-ip32.c121 .io_map_base = CKSEG1ADDR(MACEPCI_LOW_IO),
/linux-master/arch/mips/bcm47xx/
H A Dprom.c113 setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
/linux-master/arch/mips/bmips/
H A Dsetup.c34 #define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
/linux-master/arch/mips/boot/compressed/
H A Duart-16550.c15 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset))
20 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
/linux-master/arch/mips/fw/sni/
H A Dsniprom.c35 #define PROM_VEC (u64 *)CKSEG1ADDR(0x1fc00000)
87 return (void *)CKSEG1ADDR(hwconf);
/linux-master/arch/mips/include/asm/dec/
H A Dprom.h22 #define VEC_RESET (u64 *)CKSEG1ADDR(0x1fc00000)
/linux-master/arch/mips/include/asm/mach-generic/
H A Dspaces.h53 #define CKSEG1ADDR_OR_64BIT(x) CKSEG1ADDR(x)
/linux-master/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h56 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
/linux-master/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h67 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))

Completed in 446 milliseconds

12