/linux-master/drivers/soc/samsung/ |
H A D | exynos3250-pmu.c | 21 { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 26 { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 27 { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 28 { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, 29 { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, [all...] |
H A D | exynos5250-pmu.c | 21 { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 22 { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, 23 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, 29 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 30 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, 31 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, [all...] |
H A D | exynos4-pmu.c | 24 { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, 25 { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, 26 { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, 27 { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, 28 { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, 29 { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, 30 { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, 31 { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, [all...] |
/linux-master/sound/soc/codecs/ |
H A D | rt5616.h | 152 #define RT5616_L_MUTE (0x1 << 15) 154 #define RT5616_VOL_L_MUTE (0x1 << 14) 156 #define RT5616_R_MUTE (0x1 << 7) 158 #define RT5616_VOL_R_MUTE (0x1 << 6) 166 #define RT5616_EN_DFO (0x1 << 15) 174 #define RT5616_IN_DF1 (0x1 << 7) 176 #define RT5616_IN_DF2 (0x1 << 6) 182 #define RT5616_INR_SEL_MASK (0x1 << 7) 185 #define RT5616_INR_SEL_MONON (0x1 << 7) 208 #define RT5616_M_MONO_ADC_L (0x1 << 1 [all...] |
H A D | mt6358.h | 21 #define RG_VOW13M_CK_PDN_MASK 0x1 22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13) 24 #define RG_VOW32K_CK_PDN_MASK 0x1 25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12) 27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1 28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8) 30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1 31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7) 33 #define RG_AUDNCP_CK_PDN_MASK 0x1 34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << [all...] |
H A D | rt5645.h | 217 #define RT5645_L_MUTE (0x1 << 15) 219 #define RT5645_VOL_L_MUTE (0x1 << 14) 221 #define RT5645_R_MUTE (0x1 << 7) 223 #define RT5645_VOL_R_MUTE (0x1 << 6) 233 #define RT5645_CBJ_JD_HP_EN (0x1 << 9) 234 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8) 235 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7) 236 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6) 237 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5) 238 #define RT5645_CBJ_MIC_SW (0x1 << [all...] |
H A D | rt5660.h | 133 #define RT5660_L_MUTE (0x1 << 15) 135 #define RT5660_VOL_L_MUTE (0x1 << 14) 137 #define RT5660_R_MUTE (0x1 << 7) 139 #define RT5660_VOL_R_MUTE (0x1 << 6) 147 #define RT5660_IN_DF1 (0x1 << 15) 151 #define RT5660_IN_DF2 (0x1 << 7) 157 #define RT5660_IN_DF3 (0x1 << 15) 161 #define RT5660_IN_DF4 (0x1 << 7) 185 #define RT5660_M_ADC_L1 (0x1 << 14) 187 #define RT5660_M_ADC_L2 (0x1 << 1 [all...] |
H A D | rt5640.h | 183 #define RT5640_L_MUTE (0x1 << 15) 185 #define RT5640_VOL_L_MUTE (0x1 << 14) 187 #define RT5640_R_MUTE (0x1 << 7) 189 #define RT5640_VOL_R_MUTE (0x1 << 6) 207 #define RT5640_IN_DF1 (0x1 << 7) 209 #define RT5640_IN_DF2 (0x1 << 6) 213 #define RT5640_INL_SEL_MASK (0x1 << 15) 216 #define RT5640_INL_SEL_MONOP (0x1 << 15) 219 #define RT5640_INR_SEL_MASK (0x1 << 7) 222 #define RT5640_INR_SEL_MONON (0x1 << [all...] |
H A D | rt5631.h | 83 #define RT5631_L_MUTE (0x1 << 15) 85 #define RT5631_L_EN (0x1 << 14) 87 #define RT5631_R_MUTE (0x1 << 7) 89 #define RT5631_R_EN (0x1 << 6) 96 #define RT5631_SPK_L_VOL_SEL_MASK (0x1 << 14) 98 #define RT5631_SPK_L_VOL_SEL_SPKMIX_L (0x1 << 14) 99 #define RT5631_SPK_R_VOL_SEL_MASK (0x1 << 6) 101 #define RT5631_SPK_R_VOL_SEL_SPKMIX_R (0x1 << 6) 104 #define RT5631_HP_L_VOL_SEL_MASK (0x1 << 14) 106 #define RT5631_HP_L_VOL_SEL_OUTMIX_L (0x1 << 1 [all...] |
H A D | rt5651.h | 176 #define RT5651_L_MUTE (0x1 << 15) 178 #define RT5651_VOL_L_MUTE (0x1 << 14) 180 #define RT5651_R_MUTE (0x1 << 7) 182 #define RT5651_VOL_R_MUTE (0x1 << 6) 190 #define RT5651_EN_DFO (0x1 << 15) 198 #define RT5651_IN_DF1 (0x1 << 7) 200 #define RT5651_IN_DF2 (0x1 << 6) 205 #define RT5651_INL_SEL_MASK (0x1 << 15) 208 #define RT5651_INL_SEL_MONOP (0x1 << 15) 211 #define RT5651_INR_SEL_MASK (0x1 << [all...] |
H A D | rt5670.h | 213 #define RT5670_L_MUTE (0x1 << 15) 215 #define RT5670_R_MUTE (0x1 << 7) 225 #define RT5670_ID_5672 (0x1 << 1) 231 #define RT5670_CBJ_JD_HP_EN (0x1 << 9) 232 #define RT5670_CBJ_JD_MIC_EN (0x1 << 8) 233 #define RT5670_CBJ_BST1_EN (0x1 << 2) 236 #define RT5670_CBJ_MN_JD (0x1 << 12) 237 #define RT5670_CAPLESS_EN (0x1 << 11) 238 #define RT5670_CBJ_DET_MODE (0x1 << 7) 245 #define RT5670_IN_DF1 (0x1 << [all...] |
H A D | mt6359.h | 140 #define AUXADC_RQST_CH0_MASK 0x1 141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0) 145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1 146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6) 151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1 152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0) 156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1 157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1) 172 #define RG_ACCDET_CK_PDN_MASK 0x1 173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << [all...] |
/linux-master/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.h | 123 #define RESET_DP_TX (0x1 << 0) 126 #define MASTER_VID_FUNC_EN_N (0x1 << 7) 127 #define RK_VID_CAP_FUNC_EN_N (0x1 << 6) 128 #define SLAVE_VID_FUNC_EN_N (0x1 << 5) 129 #define RK_VID_FIFO_FUNC_EN_N (0x1 << 5) 130 #define AUD_FIFO_FUNC_EN_N (0x1 << 4) 131 #define AUD_FUNC_EN_N (0x1 << 3) 132 #define HDCP_FUNC_EN_N (0x1 << 2) 133 #define CRC_FUNC_EN_N (0x1 << 1) 134 #define SW_FUNC_EN_N (0x1 << [all...] |
/linux-master/drivers/usb/phy/ |
H A D | phy-fsl-usb.h | 9 #define USB_CMD_RUN_STOP (0x1<<0) 10 #define USB_CMD_CTRL_RESET (0x1<<1) 11 #define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4) 12 #define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5) 13 #define USB_CMD_INT_AA_DOORBELL (0x1<<6) 15 #define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11) 16 #define USB_CMD_SUTW (0x1<<13) 17 #define USB_CMD_ATDTW (0x1<<14) 22 #define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2) 25 #define USB_CMD_FRAME_SIZE_64 (0x1<<1 [all...] |
/linux-master/sound/soc/mediatek/mt8192/ |
H A D | mt8192-reg.h | 26 #define BCK_INVERSE_MASK 0x1 27 #define BCK_INVERSE_MASK_SFT (0x1 << 3) 31 #define VUL12_ON_MASK 0x1 32 #define VUL12_ON_MASK_SFT (0x1 << 31) 34 #define MOD_DAI_ON_MASK 0x1 35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30) 37 #define DAI_ON_MASK 0x1 38 #define DAI_ON_MASK_SFT (0x1 << 29) 40 #define DAI2_ON_MASK 0x1 41 #define DAI2_ON_MASK_SFT (0x1 << 2 [all...] |
/linux-master/drivers/gpu/drm/radeon/ |
H A D | rv250d.h | 35 #define S_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 3) 36 #define G_00000D_CP_MAX_DYN_STOP_LAT(x) (((x) >> 3) & 0x1) 38 #define S_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 4) 39 #define G_00000D_HDP_MAX_DYN_STOP_LAT(x) (((x) >> 4) & 0x1) 41 #define S_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 5) 42 #define G_00000D_TV_MAX_DYN_STOP_LAT(x) (((x) >> 5) & 0x1) 44 #define S_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 6) 45 #define G_00000D_E2_MAX_DYN_STOP_LAT(x) (((x) >> 6) & 0x1) 47 #define S_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) & 0x1) << 7) 48 #define G_00000D_SE_MAX_DYN_STOP_LAT(x) (((x) >> 7) & 0x1) [all...] |
H A D | r100d.h | 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 70 #define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1) 72 #define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1) 73 #define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1) 75 #define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2) 76 #define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1) 78 #define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3) 79 #define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1) 81 #define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4) 82 #define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1) [all...] |
H A D | rs600d.h | 33 #define S_000040_SCRATCH_INT_MASK(x) (((x) & 0x1) << 18) 34 #define G_000040_SCRATCH_INT_MASK(x) (((x) >> 18) & 0x1) 36 #define S_000040_GUI_IDLE_MASK(x) (((x) & 0x1) << 19) 37 #define G_000040_GUI_IDLE_MASK(x) (((x) >> 19) & 0x1) 39 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13) 40 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1) 42 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14) 43 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1) 45 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15) 46 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1) [all...] |
H A D | r520d.h | 41 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 42 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 44 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 45 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 47 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 48 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 50 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 51 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) 53 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9) 54 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1) [all...] |
H A D | rv350d.h | 33 #define S_00000D_FORCE_VAP(x) (((x) & 0x1) << 21) 34 #define G_00000D_FORCE_VAP(x) (((x) >> 21) & 0x1) 36 #define S_00000D_FORCE_SR(x) (((x) & 0x1) << 25) 37 #define G_00000D_FORCE_SR(x) (((x) >> 25) & 0x1) 39 #define S_00000D_FORCE_PX(x) (((x) & 0x1) << 26) 40 #define G_00000D_FORCE_PX(x) (((x) >> 26) & 0x1) 42 #define S_00000D_FORCE_TX(x) (((x) & 0x1) << 27) 43 #define G_00000D_FORCE_TX(x) (((x) >> 27) & 0x1) 45 #define S_00000D_FORCE_US(x) (((x) & 0x1) << 28) 46 #define G_00000D_FORCE_US(x) (((x) >> 28) & 0x1) [all...] |
H A D | r420d.h | 35 #define S_0001F8_MC_IND_WR_EN(x) (((x) & 0x1) << 8) 36 #define G_0001F8_MC_IND_WR_EN(x) (((x) >> 8) & 0x1) 43 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0) 44 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1) 46 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1) 47 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1) 49 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2) 50 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1) 52 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3) 53 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1) [all...] |
/linux-master/drivers/clk/visconti/ |
H A D | pll-tmpv770x.c | 22 VISCONTI_PLL_RATE(840000000, 0x1, 0x0, 0x1, 0x54, 0x000000, 0x2, 0x1), 23 VISCONTI_PLL_RATE(780000000, 0x1, 0x0, 0x1, 0x4e, 0x000000, 0x2, 0x1), 24 VISCONTI_PLL_RATE(600000000, 0x1, 0x0, 0x1, 0x3c, 0x000000, 0x2, 0x1), 29 VISCONTI_PLL_RATE(780000000, 0x1, [all...] |
/linux-master/sound/soc/mediatek/mt6797/ |
H A D | mt6797-reg.h | 263 #define AHB_IDLE_EN_INT_MASK 0x1 264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30) 266 #define AHB_IDLE_EN_EXT_MASK 0x1 267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29) 269 #define PDN_TML_MASK 0x1 270 #define PDN_TML_MASK_SFT (0x1 << 27) 272 #define PDN_DAC_PREDIS_MASK 0x1 273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26) 275 #define PDN_DAC_MASK 0x1 276 #define PDN_DAC_MASK_SFT (0x1 << 2 [all...] |
/linux-master/drivers/infiniband/hw/qib/ |
H A D | qib_7220_regs.h | 39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1 41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1 57 #define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x1 59 #define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x1 61 #define QIB_7220_Control_Reserved_RMASK 0x1 63 #define QIB_7220_Control_TxLatency_RMASK 0x1 65 #define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x1 67 #define QIB_7220_Control_LinkEn_RMASK 0x1 68 #define QIB_7220_Control_FreezeMode_LSB 0x1 69 #define QIB_7220_Control_FreezeMode_RMASK 0x1 [all...] |
/linux-master/sound/soc/mediatek/mt8183/ |
H A D | mt8183-reg.h | 418 #define BCK_INVERSE_MASK 0x1 419 #define BCK_INVERSE_MASK_SFT (0x1 << 3) 423 #define AWB2_ON_MASK 0x1 424 #define AWB2_ON_MASK_SFT (0x1 << 29) 426 #define VUL2_ON_MASK 0x1 427 #define VUL2_ON_MASK_SFT (0x1 << 27) 429 #define MOD_DAI_DUP_WR_MASK 0x1 430 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26) 435 #define VUL12_R_MONO_MASK 0x1 436 #define VUL12_R_MONO_MASK_SFT (0x1 << 1 [all...] |