Searched refs:writel_relaxed (Results 1 - 25 of 691) sorted by relevance

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/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-apq8064-sata.c91 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL);
92 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0);
97 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0);
98 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1);
99 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0);
100 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0);
101 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2);
104 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG);
105 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG);
107 writel_relaxed(
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/linux-master/drivers/clocksource/
H A Dtimer-gx6605s.c30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS);
31 writel_relaxed(0, base + TIMER_INI);
43 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
46 writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN,
58 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL);
61 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI);
62 writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL);
71 writel_relaxed(0, base + TIMER_CONTRL);
72 writel_relaxed(0, base + TIMER_CONFIG);
105 writel_relaxed(
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H A Dtimer-lpc32xx.c75 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
76 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0);
77 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR);
88 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
102 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR);
105 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R |
116 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R,
123 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR);
124 writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0);
125 writel_relaxed(LPC32XX_TIMER_TCR_CE
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H A Dtimer-milbeaut.c57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
133 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
139 writel_relaxed(0, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
/linux-master/drivers/gpu/drm/meson/
H A Dmeson_venc.c1048 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
1049 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
1056 writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10,
1058 writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) |
1063 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
1066 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
1067 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
1070 writel_relaxed(vmode->enci.hso_begin,
1072 writel_relaxed(vmode->enci.hso_end,
1076 writel_relaxed(vmod
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H A Dmeson_vpp.c59 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
62 writel_relaxed(coefs[i],
84 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0,
87 writel_relaxed(coefs[i],
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE,
101 writel_relaxed(0x1020080,
103 writel_relaxed(0x42020,
106 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
110 writel_relaxed(VPP_OFIFO_SIZE_DEFAUL
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H A Dmeson_crtc.c107 writel_relaxed(0 << 16 |
110 writel_relaxed(0 << 16 |
113 writel_relaxed(crtc_state->mode.hdisplay << 16 |
251 writel_relaxed(priv->viu.osd1_blk2_cfg4,
257 writel_relaxed(priv->viu.osd1_blk1_cfg4,
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h,
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v,
277 writel_relaxed(priv->viu.osb_blend0_size,
280 writel_relaxed(priv->viu.osb_blend1_size,
302 writel_relaxed(VD_BLEND_PREBLD_SRC_VD
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/linux-master/arch/arm/mach-mvebu/
H A Dkirkwood-pm.c25 writel_relaxed(~0, memory_pm_ctrl);
28 writel_relaxed(0x7, ddr_operation_base);
37 writel_relaxed(mem_pm_ctrl, memory_pm_ctrl);
/linux-master/drivers/media/platform/qcom/camss/
H A Dcamss-csiphy-2ph-1-0.c58 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
60 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
108 writel_relaxed(0x1, csiphy->base +
110 writel_relaxed(0x1, csiphy->base +
115 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
118 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
126 writel_relaxed(0x10, csiphy->base +
128 writel_relaxed(settle_cnt, csiphy->base +
130 writel_relaxed(0x3f, csiphy->base +
132 writel_relaxed(
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H A Dcamss-csid-gen2.c373 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG0);
377 writel_relaxed(val, csid->base + CSID_TPG_VC_CFG1);
379 writel_relaxed(0x12345678, csid->base + CSID_TPG_LFSR_SEED);
383 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_0(0));
386 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_1(0));
391 writel_relaxed(val, csid->base + CSID_TPG_DT_n_CFG_2(0));
393 writel_relaxed(0, csid->base + CSID_TPG_COLOR_BARS_CFG);
395 writel_relaxed(0, csid->base + CSID_TPG_COLOR_BOX_CFG);
406 writel_relaxed(val, csid->base + CSID_RDI_CFG0(vc));
410 writel_relaxed(va
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H A Dcamss-vfe-4-8.c263 writel_relaxed(bits & ~clr_bits, vfe->base + reg);
270 writel_relaxed(bits | set_bits, vfe->base + reg);
286 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);
290 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
295 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
301 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
385 writel_relaxed(reg, vfe->base +
394 writel_relaxed(reg, vfe->base +
397 writel_relaxed(0, vfe->base +
399 writel_relaxed(
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H A Dcamss-vfe-4-1.c234 writel_relaxed(bits & ~clr_bits, vfe->base + reg);
241 writel_relaxed(bits | set_bits, vfe->base + reg);
256 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
261 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
267 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
319 writel_relaxed(reg, vfe->base +
328 writel_relaxed(reg, vfe->base +
331 writel_relaxed(0, vfe->base +
333 writel_relaxed(0, vfe->base +
350 writel_relaxed(re
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H A Dcamss-vfe-4-7.c280 writel_relaxed(bits & ~clr_bits, vfe->base + reg);
287 writel_relaxed(bits | set_bits, vfe->base + reg);
303 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0);
307 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD);
312 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ,
318 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);
412 writel_relaxed(reg, vfe->base +
421 writel_relaxed(reg, vfe->base +
424 writel_relaxed(0, vfe->base +
426 writel_relaxed(
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/linux-master/drivers/mmc/host/
H A Dmmci_qcom_dml.c64 writel_relaxed(config, base + DML_CONFIG);
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE);
70 writel_relaxed(data->blocks * data->blksz,
75 writel_relaxed(config, base + DML_CONFIG);
77 writel_relaxed(1, base + DML_PRODUCER_START);
84 writel_relaxed(config, base + DML_CONFIG);
88 writel_relaxed(config, base + DML_CONFIG);
90 writel_relaxed(1, base + DML_CONSUMER_START);
140 writel_relaxed(1, base + DML_SW_RESET);
161 writel_relaxed(confi
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/linux-master/arch/arm/mach-aspeed/
H A Dplatsmp.c25 writel_relaxed(0, base + BOOT_ADDR);
26 writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR);
27 writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG);
/linux-master/arch/arm/mach-shmobile/
H A Dpm-rcar-gen2.c110 writel_relaxed(bar, p + CA15BAR);
111 writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
114 writel_relaxed((readl_relaxed(p + CA15RESCNT) &
119 writel_relaxed(bar, p + CA7BAR);
120 writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
123 writel_relaxed((readl_relaxed(p + CA7RESCNT) &
/linux-master/arch/arm/mach-s3c/
H A Dpm-common.c52 writel_relaxed(ptr->val, ptr->reg);
72 writel_relaxed(ptr->val, ptr->reg);
H A Dcpu.c26 writel_relaxed(0x0, S3C_VA_SYS + 0xA1C);
/linux-master/drivers/irqchip/
H A Dirq-gic-common.c81 writel_relaxed(val, base + confoff);
102 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG,
109 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
116 writel_relaxed(GICD_INT_EN_CLR_X32,
118 writel_relaxed(GICD_INT_EN_CLR_X32,
135 writel_relaxed(GICD_INT_EN_CLR_X32,
137 writel_relaxed(GICD_INT_EN_CLR_X32,
145 writel_relaxed(GICD_INT_DEF_PRI_X4,
/linux-master/arch/arm/mach-hisi/
H A Dhotplug.c82 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
87 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
92 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
95 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
99 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
106 writel_relaxed(val, ctrl_base + SCPERCTRL0);
111 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
116 writel_relaxed(val, ctrl_base + SCPERCTRL0);
119 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
123 writel_relaxed(CPU2_ISO_CTR
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/linux-master/arch/arm/mach-spear/
H A Drestart.c26 writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
/linux-master/arch/arm/mach-pxa/
H A Dreset.c75 writel_relaxed(OWER_WME, OWER);
76 writel_relaxed(OSSR_M3, OSSR);
78 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
84 writel_relaxed(MDREFR_SLFRSH, MDREFR);
/linux-master/arch/arm/mach-imx/
H A Dmach-imx51.c63 writel_relaxed(0x00000203, m4if_base + 0x40);
64 writel_relaxed(0x00000000, m4if_base + 0x44);
65 writel_relaxed(0x00120125, m4if_base + 0x9c);
66 writel_relaxed(0x001901A3, m4if_base + 0x48);
/linux-master/drivers/perf/
H A Dqcom_l3_pmu.c203 writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG);
207 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1));
208 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx));
214 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1));
215 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx));
218 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1));
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET);
220 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx));
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET);
232 writel_relaxed(PMCNTENCL
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/linux-master/drivers/mailbox/
H A Dpl320-ipc.c50 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
51 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
56 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
57 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
64 writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i));
65 writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox));
106 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
112 writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
138 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
146 writel_relaxed(CHAN_MAS
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