Searched refs:we (Results 1 - 25 of 144) sorted by relevance

123456

/linux-master/arch/arm/mach-zynq/
H A Dheadsmp.S13 ARM_BE8(setend be) @ ensure we are in BE8 mode
/linux-master/arch/x86/kernel/acpi/
H A Dwakeup_32.S22 # reload the gdt, as we need the full 32 bit address
38 # jump to place where we left off
82 # In case of S3 failure, we'll emerge here. Jump
/linux-master/arch/alpha/kernel/
H A Dhead.S30 /* ... and then we can start the kernel. */
62 # masking, and we cannot duplicate the effort without causing problems
89 # Putting it here means we dont have to recompile the whole
/linux-master/arch/arm/mm/
H A Dtlb-v4.S34 retne lr @ no, we dont do anything
H A Dtlb-v4wb.S34 retne lr @ no, we dont do anything
H A Dtlb-v4wbi.S33 retne lr @ no, we dont do anything
H A Dtlb-fa.S38 retne lr @ no, we dont do anything
/linux-master/arch/arm/mach-shmobile/
H A Dheadsmp-scu.S15 * First we turn on L1 cache coherency for our CPU. Then we jump to
23 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
/linux-master/tools/perf/
H A Dbuiltin-timechart.c86 * this is because we want to track different programs different, while
429 struct wake_event *we = zalloc(sizeof(*we)); local
431 if (!we)
434 we->time = timestamp;
435 we->waker = waker;
436 we->backtrace = backtrace;
439 we->waker = -1;
441 we->wakee = wakee;
442 we
1046 struct wake_event *we; local
[all...]
/linux-master/arch/arm/lib/
H A Ddiv64.S54 @ See if we need to handle upper 32-bit result.
93 @ See if we need to handle lower 32-bit result.
101 @ Here we shift remainer bits leftwards rather than moving the
116 @ Otherwise, if lower part is also null then we are done.
125 clz xh, xl @ we know xh is zero here so...
141 @ If no bit position left then we are done.
H A Dio-writesl.S11 teq r2, #0 @ do we have to check for the zero len?
/linux-master/arch/x86/realmode/rm/
H A Dtrampoline_32.S10 * Entry: CS:IP point to the start of our code, we are
19 * and IP is zero. Thus, we load CS to the physical segment
42 movl tr_start, %eax # where we need to go
/linux-master/arch/arm/kernel/
H A Dentry-v7m.S46 @ If we took the interrupt while running in the kernel, we may already
/linux-master/arch/arm/boot/compressed/
H A Dhead-xscale.S21 @ memory to be sure we hit the same cache.
H A Defi-header.S22 @ boot protocol does, so we need some NOPs here.
37 @ simplicity we keep it together with the MSDOS header
/linux-master/arch/powerpc/lib/
H A Ddiv64.S29 cntlzw r0,r5 # we are shifting the dividend right
39 divwu r11,r11,r9 # then we divide the shifted quantities
/linux-master/arch/arc/mm/
H A Dtlbex.S13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
54 ; [All of this dance is to avoid stack switching for each TLB Miss, since we
341 ; By now, r2 setup with all the Flags we need to check in PTE
/linux-master/arch/alpha/lib/
H A Dstrncpy.S33 bne $18, $multiword # do we have full words left?
H A Dev6-clear_user.S6 * Zero user space, handling exceptions as we go.
28 * may come along during the execution of this chunk of code, and we don't
29 * want to leave a hole (and we also want to avoid repeating lots of work)
33 /* Allow an exception for an insn; exit if we get one. */
58 # Note - we never actually use $2, so this is a moot computation
59 # and we can rewrite this later...
86 subq $1, 16, $4 # .. .. .. E : If < 16, we can not use the huge loop
92 * We know that we're going to do at least 16 quads, which means we are
94 * Figure out how many quads we nee
[all...]
H A Dstrncat.S9 * This differs slightly from the semantics in libc in that we never write
64 0: cmplt $27, $24, $2 # did we fill the buffer completely?
77 1: /* Here we must read the next DST word and clear the first byte. */
H A Dev67-strchr.S59 cttz t0, a2 # U0 : speculative (in case we get a match)
76 cttz t3, a2 # U0 : speculative (in case we get a match)
/linux-master/arch/xtensa/lib/
H A Dstrnlen_user.S50 addi a4, a2, -4 # because we overincrement at the end;
51 # we compensate with load offsets of 4
93 # Actually, we don't need to check. Zero or nonzero, we'll add one.
94 # Do not add an extra one for the NULL terminator since we have
101 # NOTE that in several places below, we point to the byte just after
/linux-master/arch/arc/kernel/
H A Dentry-compact.S30 * out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
40 * we need to explicitly do this. The problem in macros
80 * across sections (.vector to .text) we are guaranteed that 'j somewhere'
313 # reenabled after we return from interrupt/exception.
321 ; Note that we use realtime STATUS32 (not pt_regs->status32) to
343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
345 ; undeterministically. Now that we've achieved that, let's reset
357 ; must not be 0 because we would have incremented it.
358 ; If this does happen we simply HALT as it means a BUG !!!
/linux-master/arch/m68k/kernel/
H A Dsun3-head.S44 /* Make sure we're in context zero. */
64 moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it
/linux-master/arch/m68k/math-emu/
H A Dfp_entry.S80 | we jump here after an access error while trying to access
81 | user space, we correct stackpointer and send a SIGSEGV to
95 | send a trace signal if we are debugged
110 | directly, others are on the stack, as we read/write the stack

Completed in 193 milliseconds

123456