/linux-master/arch/arm/mach-zynq/ |
H A D | headsmp.S | 13 ARM_BE8(setend be) @ ensure we are in BE8 mode
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/linux-master/arch/x86/kernel/acpi/ |
H A D | wakeup_32.S | 22 # reload the gdt, as we need the full 32 bit address 38 # jump to place where we left off 82 # In case of S3 failure, we'll emerge here. Jump
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/linux-master/arch/alpha/kernel/ |
H A D | head.S | 30 /* ... and then we can start the kernel. */ 62 # masking, and we cannot duplicate the effort without causing problems 89 # Putting it here means we dont have to recompile the whole
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/linux-master/arch/arm/mm/ |
H A D | tlb-v4.S | 34 retne lr @ no, we dont do anything
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H A D | tlb-v4wb.S | 34 retne lr @ no, we dont do anything
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H A D | tlb-v4wbi.S | 33 retne lr @ no, we dont do anything
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H A D | tlb-fa.S | 38 retne lr @ no, we dont do anything
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/linux-master/arch/arm/mach-shmobile/ |
H A D | headsmp-scu.S | 15 * First we turn on L1 cache coherency for our CPU. Then we jump to 23 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
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/linux-master/tools/perf/ |
H A D | builtin-timechart.c | 86 * this is because we want to track different programs different, while 429 struct wake_event *we = zalloc(sizeof(*we)); local 431 if (!we) 434 we->time = timestamp; 435 we->waker = waker; 436 we->backtrace = backtrace; 439 we->waker = -1; 441 we->wakee = wakee; 442 we 1046 struct wake_event *we; local [all...] |
/linux-master/arch/arm/lib/ |
H A D | div64.S | 54 @ See if we need to handle upper 32-bit result. 93 @ See if we need to handle lower 32-bit result. 101 @ Here we shift remainer bits leftwards rather than moving the 116 @ Otherwise, if lower part is also null then we are done. 125 clz xh, xl @ we know xh is zero here so... 141 @ If no bit position left then we are done.
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H A D | io-writesl.S | 11 teq r2, #0 @ do we have to check for the zero len?
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/linux-master/arch/x86/realmode/rm/ |
H A D | trampoline_32.S | 10 * Entry: CS:IP point to the start of our code, we are 19 * and IP is zero. Thus, we load CS to the physical segment 42 movl tr_start, %eax # where we need to go
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/linux-master/arch/arm/kernel/ |
H A D | entry-v7m.S | 46 @ If we took the interrupt while running in the kernel, we may already
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/linux-master/arch/arm/boot/compressed/ |
H A D | head-xscale.S | 21 @ memory to be sure we hit the same cache.
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H A D | efi-header.S | 22 @ boot protocol does, so we need some NOPs here. 37 @ simplicity we keep it together with the MSDOS header
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/linux-master/arch/powerpc/lib/ |
H A D | div64.S | 29 cntlzw r0,r5 # we are shifting the dividend right 39 divwu r11,r11,r9 # then we divide the shifted quantities
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/linux-master/arch/arc/mm/ |
H A D | tlbex.S | 13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB 54 ; [All of this dance is to avoid stack switching for each TLB Miss, since we 341 ; By now, r2 setup with all the Flags we need to check in PTE
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/linux-master/arch/alpha/lib/ |
H A D | strncpy.S | 33 bne $18, $multiword # do we have full words left?
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H A D | ev6-clear_user.S | 6 * Zero user space, handling exceptions as we go. 28 * may come along during the execution of this chunk of code, and we don't 29 * want to leave a hole (and we also want to avoid repeating lots of work) 33 /* Allow an exception for an insn; exit if we get one. */ 58 # Note - we never actually use $2, so this is a moot computation 59 # and we can rewrite this later... 86 subq $1, 16, $4 # .. .. .. E : If < 16, we can not use the huge loop 92 * We know that we're going to do at least 16 quads, which means we are 94 * Figure out how many quads we nee [all...] |
H A D | strncat.S | 9 * This differs slightly from the semantics in libc in that we never write 64 0: cmplt $27, $24, $2 # did we fill the buffer completely? 77 1: /* Here we must read the next DST word and clear the first byte. */
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H A D | ev67-strchr.S | 59 cttz t0, a2 # U0 : speculative (in case we get a match) 76 cttz t3, a2 # U0 : speculative (in case we get a match)
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/linux-master/arch/xtensa/lib/ |
H A D | strnlen_user.S | 50 addi a4, a2, -4 # because we overincrement at the end; 51 # we compensate with load offsets of 4 93 # Actually, we don't need to check. Zero or nonzero, we'll add one. 94 # Do not add an extra one for the NULL terminator since we have 101 # NOTE that in several places below, we point to the byte just after
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/linux-master/arch/arc/kernel/ |
H A D | entry-compact.S | 30 * out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains 40 * we need to explicitly do this. The problem in macros 80 * across sections (.vector to .text) we are guaranteed that 'j somewhere' 313 # reenabled after we return from interrupt/exception. 321 ; Note that we use realtime STATUS32 (not pt_regs->status32) to 343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier 345 ; undeterministically. Now that we've achieved that, let's reset 357 ; must not be 0 because we would have incremented it. 358 ; If this does happen we simply HALT as it means a BUG !!!
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/linux-master/arch/m68k/kernel/ |
H A D | sun3-head.S | 44 /* Make sure we're in context zero. */ 64 moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it
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/linux-master/arch/m68k/math-emu/ |
H A D | fp_entry.S | 80 | we jump here after an access error while trying to access 81 | user space, we correct stackpointer and send a SIGSEGV to 95 | send a trace signal if we are debugged 110 | directly, others are on the stack, as we read/write the stack
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