Searched refs:valreg (Results 1 - 2 of 2) sorted by relevance
| /linux-master/arch/alpha/include/asm/ |
| H A D | extable.h | 12 * - valreg is the final target register for the load sequence
15 * Either errreg or valreg may be $31, in which case nothing happens.
21 * lda valreg, nextinsn(errreg)
33 unsigned int valreg : 5; member in struct:exception_table_entry::exception_fixup::__anon61
41 if ((_fixup)->fixup.bits.valreg != 31) \
42 map_reg((_fixup)->fixup.bits.valreg) = 0; \
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| /linux-master/arch/arm64/include/asm/ |
| H A D | assembler.h | 333 .macro tcr_set_t0sz, valreg, t0sz variable
334 bfi \valreg, \t0sz, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH variable
340 .macro tcr_set_t1sz, valreg, t1sz variable
341 bfi \valreg, \t1sz, #TCR_T1SZ_OFFSET, #TCR_TxSZ_WIDTH variable
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