Searched refs:umc_inst (Results 1 - 10 of 10) sorted by relevance

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.h45 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
47 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
52 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
53 LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
59 uint32_t umc_inst, uint32_t ch_inst, void *data);
119 uint32_t umc_inst);
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H A Dumc_v8_7.c44 uint32_t umc_inst,
47 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst;
51 uint32_t umc_inst, uint32_t ch_inst,
58 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
70 uint32_t umc_inst, uint32_t ch_inst,
77 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
95 uint32_t umc_inst = 0; local
101 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
103 umc_inst, ch_inst,
106 umc_inst, ch_ins
43 get_umc_v8_7_reg_offset(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst) argument
50 umc_v8_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
69 umc_v8_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
111 umc_v8_7_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) argument
130 umc_v8_7_ecc_info_query_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint32_t ch_inst, uint32_t umc_inst) argument
165 uint32_t umc_inst = 0; local
220 uint32_t umc_inst = 0; local
306 uint32_t umc_inst = 0; local
326 umc_v8_7_query_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint32_t umc_reg_offset, uint32_t ch_inst, uint32_t umc_inst) argument
373 uint32_t umc_inst = 0; local
421 uint32_t umc_inst = 0; local
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H A Dumc_v6_7.c47 uint32_t umc_inst,
50 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
54 umc_inst = index / 4;
57 return adev->umc.channel_offs * ch_inst + UMC_V6_7_INST_DIST * umc_inst;
95 uint32_t umc_inst, uint32_t ch_inst,
104 umc_inst, ch_inst);
106 eccinfo_table_idx = umc_inst * adev->umc.channel_inst_num + ch_inst;
119 adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst];
137 uint32_t umc_inst, uint32_t ch_inst,
146 umc_inst, ch_ins
46 get_umc_v6_7_reg_offset(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst) argument
94 umc_v6_7_ecc_info_query_correctable_error_count(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
136 umc_v6_7_ecc_info_querry_uncorrectable_error_count(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
163 umc_v6_7_ecc_info_querry_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
187 umc_v6_7_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) argument
222 umc_v6_7_ecc_info_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
261 umc_v6_7_query_correctable_error_count(struct amdgpu_device *adev, uint32_t umc_reg_offset, unsigned long *error_count, uint32_t ch_inst, uint32_t umc_inst) argument
361 umc_v6_7_reset_error_count_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
412 umc_v6_7_query_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
441 umc_v6_7_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
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H A Dumc_v6_1.c88 uint32_t umc_inst,
91 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst;
147 uint32_t umc_inst = 0; local
156 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
158 umc_inst,
259 uint32_t umc_inst = 0; local
272 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) {
274 umc_inst,
299 uint32_t umc_inst)
303 uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * ade
87 get_umc_6_reg_offset(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst) argument
295 umc_v6_1_query_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint32_t umc_reg_offset, uint32_t ch_inst, uint32_t umc_inst) argument
358 uint32_t umc_inst = 0; local
431 uint32_t umc_inst = 0; local
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H A Dumc_v8_10.c72 uint32_t umc_inst,
75 return adev->umc.channel_offs * ch_inst + UMC_8_INST_DIST * umc_inst +
80 uint32_t node_inst, uint32_t umc_inst,
85 get_umc_v8_10_reg_offset(adev, node_inst, umc_inst, ch_inst);
144 uint32_t node_inst, uint32_t umc_inst,
149 get_umc_v8_10_reg_offset(adev, node_inst, umc_inst, ch_inst);
207 uint32_t ch_inst, uint32_t umc_inst,
218 umc_inst * adev->umc.channel_inst_num +
240 retired_page_addr, channel_index, umc_inst);
245 uint32_t node_inst, uint32_t umc_inst,
70 get_umc_v8_10_reg_offset(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst) argument
79 umc_v8_10_clear_error_count_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
143 umc_v8_10_query_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
205 umc_v8_10_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst, uint32_t node_inst, uint64_t mc_umc_status) argument
244 umc_v8_10_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
294 umc_v8_10_err_cnt_init_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
335 umc_v8_10_ecc_info_query_correctable_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
354 umc_v8_10_ecc_info_query_uncorrectable_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, unsigned long *error_count) argument
379 umc_v8_10_ecc_info_query_ecc_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
401 umc_v8_10_ecc_info_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
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H A Dumc_v12_0.c35 uint32_t umc_inst,
38 uint32_t index = umc_inst * adev->umc.channel_inst_num + ch_inst;
41 umc_inst = index / 4;
44 return adev->umc.channel_offs * ch_inst + UMC_V12_0_INST_DIST * umc_inst +
49 uint32_t node_inst, uint32_t umc_inst,
54 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
136 uint32_t node_inst, uint32_t umc_inst,
150 get_umc_v12_0_reg_offset(adev, node_inst, umc_inst, ch_inst);
215 retired_page, channel_index, addr_in->ma.umc_inst);
223 retired_page, channel_index, addr_in->ma.umc_inst);
53 get_umc_v12_0_reg_offset(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst) argument
68 umc_v12_0_reset_error_count_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
155 umc_v12_0_query_error_count(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
206 umc_v12_0_mca_addr_to_pa(struct amdgpu_device *adev, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst, uint32_t node_inst, struct ta_ras_query_address_output *addr_out) argument
268 umc_v12_0_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst, uint32_t node_inst) argument
324 umc_v12_0_query_error_address(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
377 umc_v12_0_err_cnt_init_per_channel(struct amdgpu_device *adev, uint32_t node_inst, uint32_t umc_inst, uint32_t ch_inst, void *data) argument
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H A Damdgpu_umc.c33 uint32_t ch_inst, uint32_t umc_inst)
38 err_data, err_addr, ch_inst, umc_inst);
50 uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst)
75 ch_inst, umc_inst);
409 uint32_t umc_inst)
427 err_rec->mcumc_id = umc_inst;
438 uint32_t umc_inst = 0;
443 LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) {
444 ret = func(adev, node_inst, umc_inst, ch_inst, data);
447 node_inst, umc_inst, ch_ins
28 amdgpu_umc_convert_error_address(struct amdgpu_device *adev, struct ras_err_data *err_data, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) argument
46 amdgpu_umc_page_retirement_mca(struct amdgpu_device *adev, uint64_t err_addr, uint32_t ch_inst, uint32_t umc_inst) argument
391 amdgpu_umc_fill_error_record(struct ras_err_data *err_data, uint64_t err_addr, uint64_t retired_page, uint32_t channel_index, uint32_t umc_inst) argument
416 uint32_t umc_inst = 0; local
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H A Dumc_v6_7.h76 uint32_t ch_inst, uint32_t umc_inst);
H A Dta_ras_if.h147 uint32_t umc_inst; member in struct:ta_ras_mca_addr
H A Damdgpu_ras.c3830 uint32_t umc_inst = 0, ch_inst = 0;
3863 umc_inst = GET_UMC_INST(m->ipid);
3867 umc_inst, ch_inst);
3869 if (!amdgpu_umc_page_retirement_mca(adev, m->addr, ch_inst, umc_inst))
3542 uint32_t umc_inst = 0, ch_inst = 0; local

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