/linux-master/drivers/gpu/drm/amd/include/ |
H A D | v10_structs.h | 28 uint32_t reserved_0; // offset: 0 (0x0) 29 uint32_t reserved_1; // offset: 1 (0x1) 30 uint32_t reserved_2; // offset: 2 (0x2) 31 uint32_t reserved_3; // offset: 3 (0x3) 32 uint32_t reserved_4; // offset: 4 (0x4) 33 uint32_t reserved_5; // offset: 5 (0x5) 34 uint32_t reserved_6; // offset: 6 (0x6) 35 uint32_t reserved_7; // offset: 7 (0x7) 36 uint32_t reserved_8; // offset: 8 (0x8) 37 uint32_t reserved_ [all...] |
H A D | v11_structs.h | 28 uint32_t shadow_base_lo; // offset: 0 (0x0) 29 uint32_t shadow_base_hi; // offset: 1 (0x1) 30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2) 31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3) 32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4) 33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5) 34 uint32_t shadow_initialized; // offset: 6 (0x6) 35 uint32_t ib_vmid; // offset: 7 (0x7) 36 uint32_t reserved_8; // offset: 8 (0x8) 37 uint32_t reserved_ [all...] |
H A D | cik_structs.h | 28 uint32_t header; 29 uint32_t compute_dispatch_initiator; 30 uint32_t compute_dim_x; 31 uint32_t compute_dim_y; 32 uint32_t compute_dim_z; 33 uint32_t compute_start_x; 34 uint32_t compute_start_y; 35 uint32_t compute_start_z; 36 uint32_t compute_num_thread_x; 37 uint32_t compute_num_thread_ [all...] |
H A D | vi_structs.h | 28 uint32_t sdmax_rlcx_rb_cntl; 29 uint32_t sdmax_rlcx_rb_base; 30 uint32_t sdmax_rlcx_rb_base_hi; 31 uint32_t sdmax_rlcx_rb_rptr; 32 uint32_t sdmax_rlcx_rb_wptr; 33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl; 34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; 35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; 36 uint32_t sdmax_rlcx_rb_rptr_addr_hi; 37 uint32_t sdmax_rlcx_rb_rptr_addr_l [all...] |
H A D | v9_structs.h | 28 uint32_t sdmax_rlcx_rb_cntl; 29 uint32_t sdmax_rlcx_rb_base; 30 uint32_t sdmax_rlcx_rb_base_hi; 31 uint32_t sdmax_rlcx_rb_rptr; 32 uint32_t sdmax_rlcx_rb_rptr_hi; 33 uint32_t sdmax_rlcx_rb_wptr; 34 uint32_t sdmax_rlcx_rb_wptr_hi; 35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl; 36 uint32_t sdmax_rlcx_rb_rptr_addr_hi; 37 uint32_t sdmax_rlcx_rb_rptr_addr_l [all...] |
/linux-master/drivers/gpu/drm/amd/amdkfd/ |
H A D | kfd_pm4_headers_aldebaran.h | 33 uint32_t ordinal1; 38 uint32_t pasid:16; /* 0 - 15 */ 39 uint32_t single_memops:1; /* 16 */ 40 uint32_t reserved1:1; /* 17 */ 41 uint32_t debug_vmid:4; /* 18 - 21 */ 42 uint32_t new_debug:1; /* 22 */ 43 uint32_t tmz:1; /* 23 */ 44 uint32_t diq_enable:1; /* 24 */ 45 uint32_t process_quantum:7; /* 25 - 31 */ 47 uint32_t ordinal [all...] |
H A D | kfd_pm4_headers.h | 33 uint32_t reserved1:8; 35 uint32_t opcode:8; 37 uint32_t count:14; 39 uint32_t type:2; 41 uint32_t u32all; 54 uint32_t ordinal1; 59 uint32_t pasid:16; 60 uint32_t reserved1:8; 61 uint32_t diq_enable:1; 62 uint32_t process_quantu [all...] |
H A D | kfd_pm4_headers_ai.h | 32 uint32_t reserved1 : 8; /* < reserved */ 33 uint32_t opcode : 8; /* < IT opcode */ 34 uint32_t count : 14;/* < number of DWORDs - 1 in the 37 uint32_t type : 2; /* < packet identifier. 41 uint32_t u32All; 59 uint32_t ordinal1; 64 uint32_t vmid_mask:16; 65 uint32_t unmap_latency:8; 66 uint32_t reserved1:5; 69 uint32_t ordinal [all...] |
H A D | kfd_pm4_headers_vi.h | 32 uint32_t reserved1 : 8; /* < reserved */ 33 uint32_t opcode : 8; /* < IT opcode */ 34 uint32_t count : 14;/* < Number of DWORDS - 1 in the 37 uint32_t type : 2; /* < packet identifier 41 uint32_t u32All; 59 uint32_t ordinal1; 64 uint32_t vmid_mask:16; 65 uint32_t unmap_latency:8; 66 uint32_t reserved1:5; 69 uint32_t ordinal [all...] |
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_socbb.h | 27 uint32_t state; 28 uint32_t dscclk_mhz; 29 uint32_t dcfclk_mhz; 30 uint32_t socclk_mhz; 31 uint32_t dram_speed_mts; 32 uint32_t fabricclk_mhz; 33 uint32_t dispclk_mhz; 34 uint32_t phyclk_mhz; 35 uint32_t dppclk_mhz; 39 uint32_t sr_exit_time_u [all...] |
H A D | amdgpu_amdkfd_gfx_v9.h | 23 void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, 24 uint32_t sh_mem_config, 25 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 26 uint32_t sh_mem_bases, uint32_t inst); 28 unsigned int vmid, uint32_t inst); 29 int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id, 30 uint32_t inst); 31 int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, uint32_t pipe_i [all...] |
H A D | amdgpu_amdkfd_gfx_v10.h | 23 uint32_t kgd_gfx_v10_enable_debug_trap(struct amdgpu_device *adev, 25 uint32_t vmid); 26 uint32_t kgd_gfx_v10_disable_debug_trap(struct amdgpu_device *adev, 28 uint32_t vmid); 30 uint32_t trap_override, 31 uint32_t *trap_mask_supported); 32 uint32_t kgd_gfx_v10_set_wave_launch_trap_override(struct amdgpu_device *adev, 33 uint32_t vmid, 34 uint32_t trap_override, 35 uint32_t trap_mask_bit [all...] |
H A D | amdgpu_gds.h | 31 uint32_t gds_size; 32 uint32_t gws_size; 33 uint32_t oa_size; 34 uint32_t gds_compute_max_wave_id; 38 uint32_t mem_base; 39 uint32_t mem_size; 40 uint32_t gws; 41 uint32_t oa;
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H A D | amdgpu_amdkfd_aldebaran.h | 22 uint32_t kgd_aldebaran_enable_debug_trap(struct amdgpu_device *adev, 24 uint32_t vmid); 25 uint32_t kgd_aldebaran_set_wave_launch_mode(struct amdgpu_device *adev, 27 uint32_t vmid);
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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/ |
H A D | gpio_regs.h | 30 uint32_t MASK_reg; 31 uint32_t MASK_mask; 32 uint32_t MASK_shift; 33 uint32_t A_reg; 34 uint32_t A_mask; 35 uint32_t A_shift; 36 uint32_t EN_reg; 37 uint32_t EN_mask; 38 uint32_t EN_shift; 39 uint32_t Y_re [all...] |
/linux-master/drivers/gpu/drm/amd/display/modules/color/ |
H A D | luts_1d.h | 31 uint32_t custom_float_x; 32 uint32_t custom_float_y; 33 uint32_t custom_float_slope; 37 uint32_t red; 38 uint32_t green; 39 uint32_t blue; 40 uint32_t delta_red; 41 uint32_t delta_green; 42 uint32_t delta_blue; 49 uint32_t hw_points_nu [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
H A D | cursor_reg_cache.h | 9 uint32_t cur_enable: 1; 10 uint32_t reser0: 3; 11 uint32_t cur_2x_magnify: 1; 12 uint32_t reser1: 3; 13 uint32_t mode: 3; 14 uint32_t reser2: 5; 15 uint32_t pitch: 2; 16 uint32_t reser3: 6; 17 uint32_t line_per_chunk: 5; 18 uint32_t reser [all...] |
/linux-master/include/sound/sof/ |
H A D | xtensa.h | 22 uint32_t exccause; 23 uint32_t excvaddr; 24 uint32_t ps; 25 uint32_t epc1; 26 uint32_t epc2; 27 uint32_t epc3; 28 uint32_t epc4; 29 uint32_t epc5; 30 uint32_t epc6; 31 uint32_t epc [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | smu8.h | 32 uint32_t Version; 33 uint32_t ImageSize; 34 uint32_t CodeSize; 35 uint32_t HeaderSize; 36 uint32_t EntryPoint; 37 uint32_t Rtos; 38 uint32_t UcodeLoadStatus; 39 uint32_t DpmTable; 40 uint32_t FanTable; 41 uint32_t PmFuseTabl [all...] |
/linux-master/include/linux/platform_data/ |
H A D | ata-pxa.h | 13 uint32_t dma_dreq; 15 uint32_t reg_shift; 17 uint32_t irq_flags;
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/linux-master/drivers/gpu/drm/amd/display/include/ |
H A D | grph_object_ctrl_defs.h | 67 uint32_t enum_id:16; /* 1 based enum */ 73 uint32_t clk_mask_register_index; 74 uint32_t clk_en_register_index; 75 uint32_t clk_y_register_index; 76 uint32_t clk_a_register_index; 77 uint32_t data_mask_register_index; 78 uint32_t data_en_register_index; 79 uint32_t data_y_register_index; 80 uint32_t data_a_register_index; 82 uint32_t clk_mask_shif [all...] |
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
H A D | smu_v14_0_0_pmfw.h | 102 uint32_t Signature; 108 uint32_t ImageVersion; 109 uint32_t ImageVersion2; // This is repeated because DW0 cannot be written in SRAM due to HW bug. 110 uint32_t Padding0[3]; 111 uint32_t SizeFWSigned; 112 uint32_t Padding1[25]; 113 uint32_t FirmwareType; 114 uint32_t Filler[32]; 119 uint32_t DpmHandlerID : 8; 120 uint32_t ActivityMonitorI [all...] |
/linux-master/tools/firewire/ |
H A D | nosy-dump.h | 15 uint32_t timestamp; 18 uint32_t zero:24; 19 uint32_t phy_id:6; 20 uint32_t identifier:2; 24 uint32_t zero:16; 25 uint32_t gap_count:6; 26 uint32_t set_gap_count:1; 27 uint32_t set_root:1; 28 uint32_t root_id:6; 29 uint32_t identifie [all...] |
/linux-master/drivers/gpu/drm/meson/ |
H A D | meson_drv.h | 70 uint32_t osd1_ctrl_stat; 71 uint32_t osd1_ctrl_stat2; 72 uint32_t osd1_blk0_cfg[5]; 73 uint32_t osd1_blk1_cfg4; 74 uint32_t osd1_blk2_cfg4; 75 uint32_t osd1_addr; 76 uint32_t osd1_stride; 77 uint32_t osd1_height; 78 uint32_t osd1_width; 79 uint32_t osd_sc_ctrl [all...] |
/linux-master/arch/mips/include/asm/octeon/ |
H A D | cvmx-pciercx-defs.h | 55 uint32_t u32; 57 __BITFIELD_FIELD(uint32_t dpe:1, 58 __BITFIELD_FIELD(uint32_t sse:1, 59 __BITFIELD_FIELD(uint32_t rma:1, 60 __BITFIELD_FIELD(uint32_t rta:1, 61 __BITFIELD_FIELD(uint32_t sta:1, 62 __BITFIELD_FIELD(uint32_t devt:2, 63 __BITFIELD_FIELD(uint32_t mdpe:1, 64 __BITFIELD_FIELD(uint32_t fbb:1, 65 __BITFIELD_FIELD(uint32_t reserved_22_2 [all...] |