Searched refs:timer_of_base (Results 1 - 16 of 16) sorted by relevance

/linux-master/drivers/clocksource/
H A Dtimer-sprd.c84 sprd_timer_disable(timer_of_base(to));
85 sprd_timer_update_counter(timer_of_base(to), cycles);
86 sprd_timer_enable(timer_of_base(to), 0);
95 sprd_timer_disable(timer_of_base(to));
96 sprd_timer_update_counter(timer_of_base(to), timer_of_period(to));
97 sprd_timer_enable(timer_of_base(to), TIMER_CTL_PERIOD_MODE);
106 sprd_timer_disable(timer_of_base(to));
115 sprd_timer_clear_interrupt(timer_of_base(to));
118 sprd_timer_disable(timer_of_base(to));
152 sprd_timer_enable_interrupt(timer_of_base(
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H A Dtimer-npcm7xx.c61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
88 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
98 writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
103 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
114 writel(evt, timer_of_base(t
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H A Dtimer-milbeaut.c55 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
57 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
71 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
76 u32 val = readl_relaxed(timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
79 writel_relaxed(val, timer_of_base(to) + MLB_TMR_EVT_TMCSR_OFS);
84 writel_relaxed(cnt, timer_of_base(to) + MLB_TMR_EVT_TMRLR1_OFS);
129 writel_relaxed(val, timer_of_base(to) + MLB_TMR_SRC_TMCSR_OFS);
130 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR1_OFS);
131 writel_relaxed(~0, timer_of_base(to) + MLB_TMR_SRC_TMRLR2_OFS);
133 writel_relaxed(val, timer_of_base(t
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H A Dtimer-sun4i.c87 sun4i_clkevt_time_stop(timer_of_base(to), 0);
96 sun4i_clkevt_time_stop(timer_of_base(to), 0);
97 sun4i_clkevt_time_start(timer_of_base(to), 0, false);
106 sun4i_clkevt_time_stop(timer_of_base(to), 0);
107 sun4i_clkevt_time_setup(timer_of_base(to), 0, timer_of_period(to));
108 sun4i_clkevt_time_start(timer_of_base(to), 0, true);
118 sun4i_clkevt_time_stop(timer_of_base(to), 0);
119 sun4i_clkevt_time_setup(timer_of_base(to), 0, evt - TIMER_SYNC_TICKS);
120 sun4i_clkevt_time_start(timer_of_base(to), 0, false);
135 sun4i_timer_clear_interrupt(timer_of_base(t
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H A Dtimer-mediatek.c56 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
143 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
144 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
151 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
160 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
162 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
173 timer_of_base(to) + GPT_CTRL_REG(timer));
212 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
222 timer_of_base(t
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H A Dtimer-gx6605s.c28 void __iomem *base = timer_of_base(to_timer_of(ce));
40 void __iomem *base = timer_of_base(to_timer_of(ce));
55 void __iomem *base = timer_of_base(to_timer_of(ce));
69 void __iomem *base = timer_of_base(to_timer_of(ce));
98 base = timer_of_base(&to) + CLKSRC_OFFSET;
151 gx6605s_clkevt_init(timer_of_base(&to));
153 return gx6605s_clksrc_init(timer_of_base(&to) + CLKSRC_OFFSET);
H A Drenesas-ostm.c48 if (readb(timer_of_base(to) + OSTM_TE) & TE) {
49 writeb(TT, timer_of_base(to) + OSTM_TT);
56 while (readb(timer_of_base(to) + OSTM_TE) & TE)
65 writel(0, timer_of_base(to) + OSTM_CMP);
66 writeb(CTL_FREERUN, timer_of_base(to) + OSTM_CTL);
67 writeb(TS, timer_of_base(to) + OSTM_TS);
69 return clocksource_mmio_init(timer_of_base(to) + OSTM_CNT,
81 system_clock = timer_of_base(to) + OSTM_CNT;
92 writel(delta, timer_of_base(to) + OSTM_CMP);
93 writeb(CTL_ONESHOT, timer_of_base(t
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H A Dtimer-stm32.c101 writel_relaxed(0, timer_of_base(to) + TIM_DIER);
114 writel_relaxed(TIM_CR1_UDIS | TIM_CR1_CEN, timer_of_base(to) + TIM_CR1);
132 next = readl_relaxed(timer_of_base(to) + TIM_CNT) + evt;
133 writel_relaxed(next, timer_of_base(to) + TIM_CCR1);
134 now = readl_relaxed(timer_of_base(to) + TIM_CNT);
139 writel_relaxed(TIM_DIER_CC1IE, timer_of_base(to) + TIM_DIER);
167 writel_relaxed(0, timer_of_base(to) + TIM_SR);
192 writel_relaxed(UINT_MAX, timer_of_base(to) + TIM_ARR);
194 width = readl_relaxed(timer_of_base(to) + TIM_ARR);
222 writel_relaxed(prescaler - 1, timer_of_base(t
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H A Dtimer-msc313e.c95 msc313e_timer_stop(timer_of_base(timer));
104 msc313e_timer_stop(timer_of_base(timer));
105 msc313e_timer_start(timer_of_base(timer), false);
114 msc313e_timer_stop(timer_of_base(timer));
115 msc313e_timer_setup(timer_of_base(timer), timer_of_period(timer));
116 msc313e_timer_start(timer_of_base(timer), true);
125 msc313e_timer_stop(timer_of_base(timer));
126 msc313e_timer_setup(timer_of_base(timer), evt);
127 msc313e_timer_start(timer_of_base(timer), false);
187 writew(MSC313E_CLK_DIVIDER - 1, timer_of_base(t
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H A Dtimer-loongson1-pwm.c47 writel(period, timer_of_base(to) + PWM_LRC);
48 writel(period, timer_of_base(to) + PWM_HRC);
53 writel(0, timer_of_base(to) + PWM_CNTR);
58 writel((INT_EN | PWM_OE | CNT_EN), timer_of_base(to) + PWM_CTRL);
63 writel(0, timer_of_base(to) + PWM_CTRL);
70 val = readl(timer_of_base(to) + PWM_CTRL);
72 writel(val, timer_of_base(to) + PWM_CTRL);
228 ls1x_clocksource.reg_base = timer_of_base(to);
H A Dtimer-rda.c71 rda_ostimer_stop(timer_of_base(to));
80 rda_ostimer_stop(timer_of_base(to));
90 rda_ostimer_stop(timer_of_base(to));
94 rda_ostimer_start(timer_of_base(to), true, cycles_per_jiffy);
109 rda_ostimer_start(timer_of_base(to), false, evt);
121 timer_of_base(to) + RDA_TIMER_IRQ_CLR);
158 void __iomem *base = timer_of_base(&rda_ostimer_of);
H A Dtimer-mediatek-cpux.c39 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
40 return readl(timer_of_base(to) + CPUX_CON_REG);
45 writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);
46 writel(val, timer_of_base(to) + CPUX_CON_REG);
H A Dtimer-tegra.c57 void __iomem *reg_base = timer_of_base(to_timer_of(evt));
75 void __iomem *reg_base = timer_of_base(to_timer_of(evt));
84 void __iomem *reg_base = timer_of_base(to_timer_of(evt));
96 void __iomem *reg_base = timer_of_base(to_timer_of(evt));
106 void __iomem *reg_base = timer_of_base(to_timer_of(evt));
136 writel_relaxed(0, timer_of_base(to) + TIMER_PTV);
137 writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR);
196 void __iomem *reg_base = timer_of_base(&suspend_rtc_to);
262 timer_reg_base = timer_of_base(to);
H A Dtimer-imx-sysctr.c37 void __iomem *base = timer_of_base(to);
56 void __iomem *base = timer_of_base(to);
72 void __iomem *base = timer_of_base(to);
160 base = timer_of_base(&to_sysctr);
H A Dtimer-of.h49 static inline void __iomem *timer_of_base(struct timer_of *to) function
H A Dtimer-imx-tpm.c197 timer_base = timer_of_base(&to_tpm);

Completed in 171 milliseconds