Searched refs:tile0 (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/gpu/drm/xe/display/
H A Dxe_plane_initial.c56 struct xe_tile *tile0 = xe_device_get_root_tile(xe); local
69 u64 __iomem *gte = tile0->mem.ggtt->gsm;
88 if (phys_base >= tile0->mem.vram.usable_size) {
120 bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base,
H A Dxe_fb_pin.c84 struct xe_tile *tile0 = xe_device_get_root_tile(xe); local
85 struct xe_ggtt *ggtt = tile0->mem.ggtt;
100 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
105 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
110 dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
/linux-master/drivers/media/platform/verisilicon/
H A Drockchip_vpu981_hw_av1_dec.c581 int tile0, tile1; local
585 for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) {
587 int tile_id = tile1 * tile_info->tile_cols + tile0;
591 u32 x0 = tile_info->width_in_sbs_minus_1[tile0] + 1;

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