/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_tile.c | 19 * DOC: Multi-tile Design 21 * Different vendors use the term "tile" a bit differently, but in the Intel 22 * world, a 'tile' is pretty close to what most people would think of as being 24 * that's what is referred to as a "multi-tile device." In such cases, pretty 25 * much all hardware is replicated per-tile, although certain responsibilities 27 * solely by the "root tile." A multi-tile platform takes care of tying the 29 * are forwarded to the root tile, the per-tile vram is combined into a single 33 * the subset of a GPU/tile tha 84 xe_tile_alloc(struct xe_tile *tile) argument 112 xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id) argument 130 tile_ttm_mgr_init(struct xe_tile *tile) argument 159 xe_tile_init_noalloc(struct xe_tile *tile) argument 183 xe_tile_migrate_wait(struct xe_tile *tile) argument [all...] |
H A D | xe_tile.h | 13 int xe_tile_init_early(struct xe_tile *tile, struct xe_device *xe, u8 id); 14 int xe_tile_init_noalloc(struct xe_tile *tile); 16 void xe_tile_migrate_wait(struct xe_tile *tile);
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H A D | xe_tile_sysfs.h | 11 void xe_tile_sysfs_init(struct xe_tile *tile); 16 return container_of(kobj, struct kobj_tile, base)->tile;
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H A D | xe_vram_freq.h | 11 void xe_vram_freq_sysfs_init(struct xe_tile *tile);
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H A D | xe_tile_sysfs.c | 26 struct xe_tile *tile = arg; local 28 kobject_put(tile->sysfs); 31 void xe_tile_sysfs_init(struct xe_tile *tile) argument 33 struct xe_device *xe = tile_to_xe(tile); 43 kt->tile = tile; 45 err = kobject_add(&kt->base, &dev->kobj, "tile%d", tile->id); 52 tile->sysfs = &kt->base; 54 xe_vram_freq_sysfs_init(tile); [all...] |
H A D | xe_tile_sysfs_types.h | 14 * struct kobj_tile - A tile's kobject struct that connects the kobject 23 /** @tile: A pointer to the tile itself */ 24 struct xe_tile *tile; member in struct:kobj_tile
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H A D | xe_pt.h | 29 struct xe_pt *xe_pt_create(struct xe_vm *vm, struct xe_tile *tile, 32 void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm, 38 __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, 43 __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, 46 bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma);
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H A D | xe_irq.c | 53 static void unmask_and_enable(struct xe_tile *tile, u32 irqregs, u32 bits) argument 55 struct xe_gt *mmio = tile->primary_gt; 71 static void mask_and_disable(struct xe_tile *tile, u32 irqregs) argument 73 struct xe_gt *mmio = tile->primary_gt; 258 static struct xe_gt *pick_engine_gt(struct xe_tile *tile, argument 262 struct xe_device *xe = tile_to_xe(tile); 265 return tile->primary_gt; 270 return tile->media_gt; 276 return tile->media_gt; 282 return tile 286 gt_irq_handler(struct xe_tile *tile, u32 master_ctl, unsigned long *intr_dw, u32 *identity) argument 344 struct xe_tile *tile = xe_device_get_root_tile(xe); local 410 struct xe_tile *tile; local 471 gt_irq_reset(struct xe_tile *tile) argument 519 xelp_irq_reset(struct xe_tile *tile) argument 531 dg1_irq_reset(struct xe_tile *tile) argument 544 dg1_irq_reset_mstr(struct xe_tile *tile) argument 553 struct xe_tile *tile; local 573 struct xe_tile *tile; local 603 struct xe_tile *tile; local 640 struct xe_tile *tile; local [all...] |
H A D | xe_mmio.c | 168 * @tile: tile to get info for 182 * NOTE: multi-tile bases will include the tile offset. 185 static int xe_mmio_tile_vram_size(struct xe_tile *tile, u64 *vram_size, argument 188 struct xe_device *xe = tile_to_xe(tile); 189 struct xe_gt *gt = tile->primary_gt; 216 /* remove the tile offset so we have just the available size */ 224 struct xe_tile *tile; local 237 /* Get the size of the root tile' 306 struct xe_tile *tile; local [all...] |
H A D | xe_mmio.h | 29 struct xe_tile *tile = gt_to_tile(gt); local 34 return readb((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr); 39 struct xe_tile *tile = gt_to_tile(gt); local 44 return readw((reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr); 50 struct xe_tile *tile = gt_to_tile(gt); local 55 writel(val, (reg.ext ? tile->mmio_ext.regs : tile->mmio.regs) + reg.addr); 60 struct xe_tile *tile local [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
H A D | nv25.c | 31 struct nvkm_fb_tile *tile) 35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { 36 if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ 37 else tile->zcomp = 0x00200000; /* Z24S8 */ 38 tile->zcomp |= tile->tag->offset; 40 tile->zcomp |= 0x01000000; 48 .tile.regions = 8, 49 .tile.init = nv20_fb_tile_init, 50 .tile 30 nv25_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv20.c | 31 u32 flags, struct nvkm_fb_tile *tile) 33 tile->addr = 0x00000001 | addr; 34 tile->limit = max(1u, addr + size) - 1; 35 tile->pitch = pitch; 37 fb->func->tile.comp(fb, i, size, flags, tile); 38 tile->addr |= 2; 44 struct nvkm_fb_tile *tile) 48 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { 49 if (!(flags & 2)) tile 30 nv20_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument 43 nv20_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument 60 nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument 70 nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv46.c | 31 u32 flags, struct nvkm_fb_tile *tile) 34 if (!(flags & 4)) tile->addr = (0 << 3); 35 else tile->addr = (1 << 3); 37 tile->addr |= 0x00000001; /* mode = vram */ 38 tile->addr |= addr; 39 tile->limit = max(1u, addr + size) - 1; 40 tile->pitch = pitch; 46 .tile.regions = 15, 47 .tile.init = nv46_fb_tile_init, 48 .tile 30 nv46_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv10.c | 31 u32 flags, struct nvkm_fb_tile *tile) 33 tile->addr = 0x80000000 | addr; 34 tile->limit = max(1u, addr + size) - 1; 35 tile->pitch = pitch; 39 nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument 41 tile->addr = 0; 42 tile->limit = 0; 43 tile->pitch = 0; 44 tile->zcomp = 0; 48 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument 30 nv10_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv1a.c | 31 .tile.regions = 8, 32 .tile.init = nv10_fb_tile_init, 33 .tile.fini = nv10_fb_tile_fini, 34 .tile.prog = nv10_fb_tile_prog,
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H A D | nv4e.c | 32 .tile.regions = 12, 33 .tile.init = nv46_fb_tile_init, 34 .tile.fini = nv20_fb_tile_fini, 35 .tile.prog = nv44_fb_tile_prog,
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H A D | nv49.c | 33 .tile.regions = 15, 34 .tile.init = nv30_fb_tile_init, 35 .tile.comp = nv40_fb_tile_comp, 36 .tile.fini = nv20_fb_tile_fini, 37 .tile.prog = nv41_fb_tile_prog,
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H A D | nv47.c | 33 .tile.regions = 15, 34 .tile.init = nv30_fb_tile_init, 35 .tile.comp = nv40_fb_tile_comp, 36 .tile.fini = nv20_fb_tile_fini, 37 .tile.prog = nv41_fb_tile_prog,
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H A D | nv36.c | 31 struct nvkm_fb_tile *tile) 35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { 36 if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ 37 else tile->zcomp |= 0x20000000; /* Z24S8 */ 38 tile->zcomp |= ((tile->tag->offset ) >> 6); 39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; 41 tile->zcomp |= 0x80000000; 50 .tile 30 nv36_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv35.c | 31 struct nvkm_fb_tile *tile) 35 if (!nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { 36 if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ 37 else tile->zcomp |= 0x08000000; /* Z24S8 */ 38 tile->zcomp |= ((tile->tag->offset ) >> 6); 39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; 41 tile->zcomp |= 0x40000000; 50 .tile 30 nv35_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv40.c | 31 struct nvkm_fb_tile *tile) 36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { 37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ 38 tile->zcomp |= ((tile->tag->offset ) >> 8); 39 tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; 41 tile->zcomp |= 0x40000000; 56 .tile.regions = 8, 57 .tile 30 nv40_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv44.c | 31 u32 flags, struct nvkm_fb_tile *tile) 33 tile->addr = 0x00000001; /* mode = vram */ 34 tile->addr |= addr; 35 tile->limit = max(1u, addr + size) - 1; 36 tile->pitch = pitch; 40 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument 43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); 44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); 45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); 60 .tile 30 nv44_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
H A D | nv41.c | 30 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile) argument 33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); 34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); 35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); 37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); 50 .tile.regions = 12, 51 .tile.init = nv30_fb_tile_init, 52 .tile.comp = nv40_fb_tile_comp, 53 .tile.fini = nv20_fb_tile_fini, 54 .tile [all...] |
H A D | nv30.c | 31 u32 flags, struct nvkm_fb_tile *tile) 35 tile->addr = (0 << 4); 37 if (fb->func->tile.comp) /* z compression */ 38 fb->func->tile.comp(fb, i, size, flags, tile); 39 tile->addr = (1 << 4); 42 tile->addr |= 0x00000001; /* enable */ 43 tile->addr |= addr; 44 tile->limit = max(1u, addr + size) - 1; 45 tile 30 nv30_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) argument 49 nv30_fb_tile_comp(struct nvkm_fb *fb, int i, u32 size, u32 flags, struct nvkm_fb_tile *tile) argument [all...] |
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
H A D | nv44.c | 31 nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile) argument 44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); 45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); 46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); 53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); 54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); 55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); 56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); 57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); 58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile [all...] |