Searched refs:t3_read_reg (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/net/ethernet/chelsio/cxgb3/
H A Dxgmac.c61 t3_read_reg(adap, ctrl);
103 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
140 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
168 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
172 store = t3_read_reg(adap, A_TP_TX_DROP_CFG_CH0 + idx);
190 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
200 t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
269 u32 v = t3_read_reg(mac->adapter, reg);
272 t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
280 u32 v = t3_read_reg(ma
[all...]
H A Dt3_hw.c60 u32 val = t3_read_reg(adapter, reg);
107 u32 v = t3_read_reg(adapter, addr) & ~mask;
110 t3_read_reg(adapter, addr); /* flush */
131 *vals++ = t3_read_reg(adap, data_reg);
169 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
171 val = t3_read_reg(adap,
176 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
178 val64 = t3_read_reg(adap,
224 ret = t3_read_reg(adapter, A_MI1_DATA);
287 ret = t3_read_reg(adapte
[all...]
H A Dcxgb3_offload.c214 uiip->llimit = t3_read_reg(adapter, A_ULPRX_ISCSI_LLIMIT);
215 uiip->ulimit = t3_read_reg(adapter, A_ULPRX_ISCSI_ULIMIT);
216 uiip->tagmask = t3_read_reg(adapter, A_ULPRX_ISCSI_TAGMASK);
218 val = t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ);
222 val = t3_read_reg(adapter, A_TP_PARA_REG7);
231 t3_read_reg(adapter, A_PM1_TX_CFG) >> 17);
235 val = t3_read_reg(adapter, A_TP_PARA_REG2);
249 ((t3_read_reg(adapter, A_TP_PARA_REG2)) >>
258 if (val && (val != t3_read_reg(adapter, A_ULPRX_ISCSI_PSZ))) {
287 t3_read_reg(adapte
[all...]
H A Dmc5.c135 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
322 cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
370 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
411 u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
H A Dael1002.c897 status = t3_read_reg(phy->adapter,
899 t3_read_reg(phy->adapter,
901 t3_read_reg(phy->adapter,
903 t3_read_reg(phy->adapter,
H A Dadapter.h270 static inline u32 t3_read_reg(struct adapter *adapter, u32 reg_addr) function
H A Dcxgb3_main.c215 t3_read_reg(adap, A_XGM_INT_STATUS +
269 t3_read_reg(adapter, A_XGM_INT_STATUS +
285 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
293 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
808 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
1459 t3_read_reg(adapter, A_XGM_INT_STATUS + pi->mac.offset);
1732 *p++ = t3_read_reg(ap, start);
2672 t3_read_reg(adapter, A_XGM_INT_STATUS + p->mac.offset);
2751 cause = t3_read_reg(adapter, A_XGM_INT_CAUSE + mac->offset);
2764 status = t3_read_reg(adapte
[all...]
H A Dsge.c2732 t3_read_reg(adap, A_PL_CLI); /* flush */
2762 map = t3_read_reg(adap, A_SG_DATA_INTR);
2797 map = t3_read_reg(adap, A_SG_DATA_INTR);
2854 unsigned int v, status = t3_read_reg(adapter, A_SG_INT_CAUSE) &
2868 v = t3_read_reg(adapter, A_SG_RSPQ_FL_STATUS);
2965 status = t3_read_reg(adap, A_SG_RSPQ_FL_STATUS);

Completed in 157 milliseconds