Searched refs:set_mask (Results 1 - 25 of 28) sorted by relevance

12

/linux-master/arch/arm64/mm/
H A Dpageattr.c17 pgprot_t set_mask; member in struct:page_change_data
42 pte = set_pte_bit(pte, cdata->set_mask);
52 pgprot_t set_mask, pgprot_t clear_mask)
57 data.set_mask = set_mask;
68 pgprot_t set_mask, pgprot_t clear_mask)
108 if (rodata_full && (pgprot_val(set_mask) == PTE_RDONLY ||
112 PAGE_SIZE, set_mask, clear_mask);
122 return __change_memory_common(start, size, set_mask, clear_mask);
168 .set_mask
51 __change_memory_common(unsigned long start, unsigned long size, pgprot_t set_mask, pgprot_t clear_mask) argument
67 change_memory_common(unsigned long addr, int numpages, pgprot_t set_mask, pgprot_t clear_mask) argument
[all...]
/linux-master/arch/arm/mm/
H A Dpageattr.c12 pgprot_t set_mask; member in struct:page_change_data
22 pte = set_pte_bit(pte, cdata->set_mask);
39 pgprot_t set_mask, pgprot_t clear_mask)
44 data.set_mask = set_mask;
55 pgprot_t set_mask, pgprot_t clear_mask)
70 return __change_memory_common(start, size, set_mask, clear_mask);
38 __change_memory_common(unsigned long start, unsigned long size, pgprot_t set_mask, pgprot_t clear_mask) argument
54 change_memory_common(unsigned long addr, int numpages, pgprot_t set_mask, pgprot_t clear_mask) argument
/linux-master/drivers/hwmon/
H A Dlm75.c60 * @set_mask: Bits to set in configuration register when configuring
85 u16 set_mask; member in struct:lm75_params
138 .set_mask = 0x94C0, /* 8 sample/s, 4 CF, positive polarity */
146 .set_mask = 3 << 5, /* 12-bit mode*/
155 .set_mask = 2 << 5, /* 11-bit mode */
164 .set_mask = 2 << 5, /* 11-bit mode */
173 .set_mask = 2 << 5, /* 11-bit mode */
185 .set_mask = 3 << 5, /* 12-bit mode*/
235 .set_mask = 3 << 5, /* 12-bit mode */
245 .set_mask
335 lm75_write_config(struct lm75_data *data, u16 set_mask, u16 clr_mask) argument
[all...]
H A Dmax31730.c60 static int max31730_write_config(struct max31730_data *data, u8 set_mask, argument
67 value |= set_mask;
/linux-master/drivers/gpio/
H A Dgpio-mmio.c150 unsigned long set_mask = 0; local
155 set_mask = *mask & gc->bgpio_dir;
158 if (set_mask)
159 *bits |= gc->read_reg(gc->reg_set) & set_mask;
264 unsigned long *set_mask,
269 *set_mask = 0;
274 *set_mask |= bgpio_line2mask(gc, i);
286 unsigned long set_mask, clear_mask; local
290 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
292 gc->bgpio_data |= set_mask;
262 bgpio_multiple_get_masks(struct gpio_chip *gc, unsigned long *mask, unsigned long *bits, unsigned long *set_mask, unsigned long *clear_mask) argument
316 unsigned long set_mask, clear_mask; local
[all...]
H A Dgpiolib.h100 * @set_mask: Set mask used in fastpath
112 unsigned long *set_mask; member in struct:gpio_array
H A Dgpiolib.c3335 gpio_chip_set_multiple(array_info->chip, array_info->set_mask,
3338 i = find_first_zero_bit(array_info->set_mask, array_size);
3408 i = find_next_zero_bit(array_info->set_mask,
4591 array_info->set_mask = array_info->get_mask +
4599 bitmap_set(array_info->set_mask, descs->ndescs,
4611 __clear_bit(descs->ndescs, array_info->set_mask);
4629 array_info->set_mask);
4636 array_info->set_mask);
4645 "GPIO array info: chip=%s, size=%d, get_mask=%lx, set_mask=%lx, invert_mask=%lx\n",
4647 *array_info->get_mask, *array_info->set_mask,
[all...]
/linux-master/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c88 u64 set_mask = 0; local
91 set_mask |= get_restricted_features_unsigned(id_aa64pfr0_el1_sys_val,
94 return (id_aa64pfr0_el1_sys_val & allow_mask) | set_mask;
189 u64 set_mask; local
191 set_mask = get_restricted_features_unsigned(id_aa64mmfr0_el1_sys_val,
194 return (id_aa64mmfr0_el1_sys_val & PVM_ID_AA64MMFR0_ALLOW) | set_mask;
/linux-master/drivers/net/ethernet/microchip/
H A Dencx24j600-regmap.c195 unsigned int set_mask = mask & val; local
201 if (set_mask & 0xff)
202 ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
204 set_mask = (set_mask & 0xff00) >> 8;
206 if ((set_mask & 0xff) && (ret == 0))
207 ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
/linux-master/drivers/net/ethernet/ibm/
H A Dibmveth.h73 unsigned long reset_mask, unsigned long set_mask,
80 reset_mask, set_mask);
72 h_illan_attributes(unsigned long unit_address, unsigned long reset_mask, unsigned long set_mask, unsigned long *ret_attributes) argument
/linux-master/drivers/mfd/
H A Dssbi.c94 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) argument
101 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
/linux-master/arch/riscv/mm/
H A Dpageattr.c14 pgprot_t set_mask; member in struct:pageattr_masks
24 new_val |= (pgprot_val(masks->set_mask));
262 static int __set_memory(unsigned long addr, int numpages, pgprot_t set_mask, argument
271 .set_mask = set_mask,
/linux-master/sound/soc/bcm/
H A Dcygnus-pcm.c348 u32 set_mask; local
355 set_mask = BIT(aio->portnum);
359 writel(set_mask, aio->cygaud->audio + ESR0_MASK_SET_OFFSET);
360 writel(set_mask, aio->cygaud->audio + ESR1_MASK_SET_OFFSET);
361 writel(set_mask, aio->cygaud->audio + ESR3_MASK_SET_OFFSET);
363 writel(set_mask, aio->cygaud->audio + ESR2_MASK_SET_OFFSET);
364 writel(set_mask, aio->cygaud->audio + ESR4_MASK_SET_OFFSET);
/linux-master/drivers/mailbox/
H A Dpcc.c72 * @set_mask: bitmask to set when writing to this register
79 u64 set_mask; member in struct:pcc_chan_reg
208 val |= reg->set_mask;
474 u64 preserve_mask, u64 set_mask, u64 status_mask, char *name)
492 reg->set_mask = set_mask;
473 pcc_chan_reg_init(struct pcc_chan_reg *reg, struct acpi_generic_address *gas, u64 preserve_mask, u64 set_mask, u64 status_mask, char *name) argument
/linux-master/sound/pci/ice1712/
H A Dice1712.h354 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data); member in struct:snd_ice1712::ice1712_gpio
407 ice->gpio.set_mask(ice, bits);
435 ice->gpio.set_mask(ice, ice->gpio.saved[1]);
H A Dquartet.c272 ice->gpio.set_mask(ice, ~GPIO_SPI_ALL);
314 ice->gpio.set_mask(ice, 0xffffff);
405 ice->gpio.set_mask(ice, ~(tmp));
429 ice->gpio.set_mask(ice, 0xffffff);
/linux-master/arch/arm/mach-omap2/
H A Dcommon.h245 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_hw_data.c454 goto set_mask;
483 set_mask:
/linux-master/drivers/net/phy/
H A Dbcm7xxx.c224 int set_mask, int clr_mask)
233 v |= set_mask;
243 int set_mask, int clr_mask)
248 ret = __phy_set_clr_bits(dev, location, set_mask, clr_mask);
223 __phy_set_clr_bits(struct phy_device *dev, int location, int set_mask, int clr_mask) argument
242 phy_set_clr_bits(struct phy_device *dev, int location, int set_mask, int clr_mask) argument
/linux-master/net/iucv/
H A Diucv.c269 struct iucv_cmd_set_mask set_mask; member in union:iucv_param
378 parm->set_mask.ipmask = 0xf8;
391 parm->set_mask.ipmask = 0xf8;
/linux-master/drivers/infiniband/hw/mlx5/
H A Dfs.c108 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask) argument
110 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
114 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
118 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
122 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
H A Dqp.c70 u32 set_mask; /* raw_qp_set_mask_map */ member in struct:mlx5_modify_raw_qp_param
3800 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
3847 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
3926 if (raw_qp_param->set_mask & ~MLX5_RAW_QP_RATE_LIMIT)
3934 if (raw_qp_param->set_mask)
4343 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
4374 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
/linux-master/drivers/s390/scsi/
H A Dzfcp_erp.c597 * @set_mask: ERP action status flags to set.
599 void zfcp_erp_notify(struct zfcp_erp_action *erp_action, unsigned long set_mask) argument
606 erp_action->status |= set_mask;
/linux-master/drivers/pinctrl/
H A Dpinctrl-at91.c1473 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); local
1476 writel_relaxed(set_mask, pio + PIO_SODR);
/linux-master/fs/btrfs/
H A Dioctl.c4277 u64 set_mask = flags & change_mask; local
4280 unsupported = set_mask & ~supported_flags;
4295 disallowed = set_mask & ~safe_set;

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