Searched refs:set_bits (Results 1 - 25 of 51) sorted by relevance

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/linux-master/tools/perf/bench/
H A Dfind-bit-bench.c63 unsigned int set_bits, skip; local
68 for (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) {
70 skip = num_bits / set_bits;
85 assert(old + (inner_iterations * set_bits) == accumulator);
101 assert(old + (inner_iterations * set_bits) == accumulator);
108 inner_iterations, set_bits, num_bits);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_reg_sr_types.h17 u32 set_bits; member in struct:xe_reg_sr_entry
H A Dxe_reg_sr.c73 * Don't allow overwriting values: clr_bits/set_bits should be disjoint
76 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits ||
77 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits)
108 pentry->set_bits |= e->set_bits;
130 idx, e->clr_bits, e->set_bits,
173 * - Masked registers can't have set_bits with upper bits set
174 * - set_bits mus
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H A Dxe_rtp.h195 .clr_bits = ~0u, .set_bits = (val_), \
213 .clr_bits = val_, .set_bits = val_, \
231 .clr_bits = val_, .set_bits = 0, \
248 .clr_bits = mask_bits_, .set_bits = val_, \
253 .clr_bits = (mask_bits_), .set_bits = (val_), \
268 .set_bits = val_, \
H A Dxe_rtp_types.h30 /** @set_bits: bits to set when updating register */
31 u32 set_bits; member in struct:xe_rtp_action
H A Dxe_reg_whitelist.c97 u32 val = entry->set_bits;
H A Dxe_rtp.c120 .set_bits = action->set_bits,
/linux-master/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) argument
79 writel(bits | set_bits, ctx->base + offset);
/linux-master/drivers/media/platform/ti/omap3isp/
H A Disp.h327 * @set_bits: 32 bit value which would be set in the register.
331 u32 reg, u32 set_bits)
335 isp_reg_writel(isp, v | set_bits, mmio_range, reg);
344 * @set_bits: 32 bit value which would be set in the register.
350 u32 reg, u32 clr_bits, u32 set_bits)
354 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg);
330 isp_reg_set(struct isp_device *isp, enum isp_mem_resources mmio_range, u32 reg, u32 set_bits) argument
349 isp_reg_clr_set(struct isp_device *isp, enum isp_mem_resources mmio_range, u32 reg, u32 clr_bits, u32 set_bits) argument
/linux-master/arch/arm/mach-omap2/
H A Domap-secure.c185 * @set_bits: bits to set in ACR
190 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) argument
197 acr |= set_bits;
H A Domap-secure.h77 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
/linux-master/fs/netfs/
H A Dfscache_io.c168 bool set_bits; member in struct:fscache_write_request
201 wreq->set_bits);
233 wreq->set_bits = cond;
/linux-master/drivers/tty/serial/
H A Dip22zilog.c546 unsigned char set_bits, clear_bits; local
548 set_bits = clear_bits = 0;
551 set_bits |= RTS;
555 set_bits |= DTR;
560 up->curregs[R5] |= set_bits;
657 unsigned char set_bits, clear_bits, new_reg; local
660 set_bits = clear_bits = 0;
663 set_bits |= SND_BRK;
669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
H A Dpmac_zilog.c516 unsigned char set_bits, clear_bits; local
525 set_bits = clear_bits = 0;
529 set_bits |= RTS;
534 set_bits |= DTR;
539 uap->curregs[R5] |= set_bits;
544 set_bits, clear_bits, uap->curregs[R5]);
664 unsigned char set_bits, clear_bits, new_reg; local
667 set_bits = clear_bits = 0;
670 set_bits |= SND_BRK;
676 new_reg = (uap->curregs[R5] | set_bits)
[all...]
H A Dsunzilog.c646 unsigned char set_bits, clear_bits; local
648 set_bits = clear_bits = 0;
651 set_bits |= RTS;
655 set_bits |= DTR;
660 up->curregs[R5] |= set_bits;
757 unsigned char set_bits, clear_bits, new_reg; local
760 set_bits = clear_bits = 0;
763 set_bits |= SND_BRK;
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
/linux-master/arch/powerpc/kernel/
H A Dsyscall.c88 set_bits(_TIF_RESTOREALL, &current_thread_info()->flags);
/linux-master/arch/powerpc/include/asm/
H A Dbitops.h82 DEFINE_BITOP(set_bits, or, "")
131 set_bits(BIT_MASK(nr), addr + BIT_WORD(nr));
/linux-master/arch/arm/mach-ep93xx/
H A Dsoc.h200 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c347 u32 set_bits = 0; local
371 set_bits |= (1 << bit);
383 vgpu_vreg(vgpu, isr) |= set_bits;
390 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
/linux-master/drivers/hwmon/
H A Dgl518sm.c299 #define set_bits(type, suffix, value, reg, mask, shift) \ macro
322 set_bits(type, suffix, value, reg, 0x00ff, 0)
324 set_bits(type, suffix, value, reg, 0xff00, 8)
328 set_bits(BOOL, fan_auto1, fan_auto1, GL518_REG_MISC, 0x08, 3);
337 set_bits(BOOL, beep_enable, beep_enable, GL518_REG_CONF, 0x04, 2);
/linux-master/drivers/gpio/
H A Dgpio-thunderx.c276 u64 set_bits, clear_bits; local
280 set_bits = bits[bank] & mask[bank];
282 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
/linux-master/include/trace/events/
H A Dbtrfs.h2086 u64 start, u64 len, unsigned set_bits),
2088 TP_ARGS(tree, start, len, set_bits),
2096 __field( unsigned, set_bits)
2107 __entry->set_bits = set_bits;
2111 "io_tree=%s ino=%llu root=%llu start=%llu len=%llu set_bits=%s",
2114 __print_flags(__entry->set_bits, "|", EXTENT_FLAGS))
2152 u64 start, u64 len, unsigned set_bits, unsigned clear_bits),
2154 TP_ARGS(tree, start, len, set_bits, clear_bits),
2162 __field( unsigned, set_bits)
[all...]
/linux-master/drivers/firewire/
H A Dcore.h65 int clear_bits, int set_bits);
/linux-master/drivers/gpu/drm/xe/tests/
H A Dxe_rtp_test.c259 KUNIT_EXPECT_EQ(test, sr_entry->set_bits, param->expected_set_bits);
/linux-master/drivers/net/ethernet/smsc/
H A Dsmc91c92_cs.c262 #define set_bits(v, p) outw(inw(p)|(v), (p)) macro
702 set_bits(0x300, link->resource[0]->start + OSITECH_AUI_PWR);
704 set_bits(0x300, link->resource[0]->start + OSITECH_RESET_ISR);
736 set_bits(0x0300, dev->base_addr-0x10+OSITECH_AUI_PWR);
737 set_bits(0x0300, dev->base_addr-0x10+OSITECH_RESET_ISR);
1442 set_bits(0x0300, ioaddr-0x10+OSITECH_RESET_ISR);
1627 set_bits(OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR);

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