Searched refs:sclk_setting (Results 1 - 3 of 3) sorted by relevance

/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c720 uint32_t clock, SMU_SclkSetting *sclk_setting)
731 sclk_setting->SclkFrequency = clock;
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
738 sclk_setting->PllRange = dividers.ucSclkPllRange;
739 sclk_setting->Sclk_slew_rate = 0x400;
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
741 sclk_setting->Pcc_down_slew_rate = 0xffff;
742 sclk_setting
719 vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, SMU_SclkSetting *sclk_setting) argument
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H A Dpolaris10_smumgr.c891 uint32_t clock, SMU_SclkSetting *sclk_setting)
902 sclk_setting->SclkFrequency = clock;
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
909 sclk_setting->PllRange = dividers.ucSclkPllRange;
910 sclk_setting->Sclk_slew_rate = 0x400;
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
912 sclk_setting->Pcc_down_slew_rate = 0xffff;
913 sclk_setting
890 polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, SMU_SclkSetting *sclk_setting) argument
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/linux-master/drivers/gpu/drm/amd/include/
H A Datomfirmware.h3951 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; member in union:dynamic_memory_settings_parameters_v2_1

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