Searched refs:sclk_mask (Results 1 - 5 of 5) sorted by relevance
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
H A D | renoir_ppt.c | 252 uint32_t *sclk_mask, 258 if (sclk_mask) 259 *sclk_mask = 0; 265 if (sclk_mask) 267 *sclk_mask = 3 - 1; 935 uint32_t sclk_mask, mclk_mask, soc_mask; local 1016 &sclk_mask, 1021 renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask); 250 renoir_get_profiling_clk_mask(struct smu_context *smu, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | vega12_hwmgr.c | 1718 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 1725 *sclk_mask = 0; 1732 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL; 1738 *sclk_mask = 0; 1742 *sclk_mask = gfx_dpm_table->count - 1; 1772 uint32_t sclk_mask = 0; local 1790 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 1793 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 1717 vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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H A D | vega20_hwmgr.c | 2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 2530 *sclk_mask = 0; 2537 *sclk_mask = VEGA20_UMD_PSTATE_GFXCLK_LEVEL; 2543 *sclk_mask = 0; 2547 *sclk_mask = gfx_dpm_table->count - 1; 2723 uint32_t sclk_mask, mclk_mask, soc_mask; local 2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 2745 vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); 2522 vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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H A D | vega10_hwmgr.c | 4183 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) 4191 *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; 4197 *sclk_mask = 0; 4205 *sclk_mask = 4; 4207 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 4300 uint32_t sclk_mask = 0; local 4318 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); 4321 vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 4182 vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) argument
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H A D | smu7_hwmgr.c | 3170 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) 3200 *sclk_mask = count; 3205 *sclk_mask = 0; 3208 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 3215 *sclk_mask = count; 3220 *sclk_mask = 0; 3223 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 3240 uint32_t sclk_mask = 0; local 3258 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 3261 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 3169 smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) argument [all...] |
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