Searched refs:reset (Results 1 - 25 of 2243) sorted by relevance

1234567891011>>

/linux-master/drivers/reset/sti/
H A DMakefile2 obj-$(CONFIG_STIH407_RESET) += reset-stih407.o reset-syscfg.o
H A Dreset-syscfg.h11 #include <linux/reset-controller.h>
15 * reset controller.
19 * @reset: Regmap field description of the channel's reset bit.
24 struct reg_field reset; member in struct:syscfg_reset_channel_data
30 .reset = REG_FIELD(_rr, _rb, _rb), \
35 .reset = REG_FIELD(_rr, _rb, _rb), }
38 * Description of a system configuration register based reset controller.
40 * @wait_for_ack: The controller will wait for reset assert and de-assert to
43 * the reset bi
[all...]
/linux-master/drivers/reset/tegra/
H A DMakefile2 obj-$(CONFIG_RESET_TEGRA_BPMP) += reset-bpmp.o
/linux-master/drivers/reset/
H A DMakefile7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
10 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
11 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
12 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
13 obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o
14 obj-$(CONFIG_RESET_GPIO) += reset-gpio.o
15 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
16 obj-$(CONFIG_RESET_IMX7) += reset
[all...]
H A Dreset-sunplus.c3 * SP7021 reset driver
13 #include <linux/reset-controller.h>
115 struct sp_reset *reset = to_sp_reset(rcdev); local
121 writel(val, reset->base + (index * 4));
141 struct sp_reset *reset = to_sp_reset(rcdev); local
146 reg = readl(reset->base + (index * 4));
160 struct sp_reset *reset = container_of(nb, struct sp_reset, notifier); local
162 sp_reset_assert(&reset->rcdev, 0);
163 sp_reset_deassert(&reset->rcdev, 0);
171 struct sp_reset *reset; local
[all...]
/linux-master/drivers/reset/starfive/
H A DMakefile2 obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
4 obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
5 obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
/linux-master/drivers/power/
H A DMakefile2 obj-$(CONFIG_POWER_RESET) += reset/
/linux-master/arch/mips/lantiq/falcon/
H A DMakefile2 obj-y := prom.o reset.o sysctrl.o
/linux-master/arch/mips/pic32/common/
H A DMakefile6 obj-y = reset.o irq.o
/linux-master/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_async_ids_map_extended.h27 int reset; member in struct:gaudi2_async_events_ids_map
32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE,
48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset
[all...]
/linux-master/drivers/clk/visconti/
H A Dreset.c3 * Toshiba Visconti ARM SoC reset controller
16 #include "reset.h"
25 struct visconti_reset *reset = to_visconti_reset(rcdev); local
26 const struct visconti_reset_data *data = &reset->resets[id];
31 spin_lock_irqsave(reset->lock, flags);
32 ret = regmap_update_bits(reset->regmap, data->rson_offset, rst, rst);
33 spin_unlock_irqrestore(reset->lock, flags);
40 struct visconti_reset *reset = to_visconti_reset(rcdev); local
41 const struct visconti_reset_data *data = &reset->resets[id];
46 spin_lock_irqsave(reset
64 struct visconti_reset *reset = to_visconti_reset(rcdev); local
93 struct visconti_reset *reset; local
[all...]
H A DMakefile4 obj-y += clkc.o pll.o reset.o
/linux-master/drivers/gpu/drm/i915/selftests/
H A Digt_reset.c19 pr_debug("%s: current gpu_error=%08lx\n", __func__, gt->reset.flags);
21 while (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags))
22 wait_event(gt->reset.queue,
23 !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
27 &gt->reset.flags))
28 wait_on_bit(&gt->reset.flags, I915_RESET_ENGINE + id,
39 clear_and_wake_up_bit(I915_RESET_ENGINE + id, &gt->reset.flags);
41 clear_bit(I915_RESET_BACKOFF, &gt->reset.flags);
42 wake_up_all(&gt->reset.queue);
/linux-master/drivers/reset/hisilicon/
H A DMakefile3 obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
/linux-master/arch/mips/loongson2ef/fuloong-2e/
H A DMakefile6 obj-y += irq.o reset.o dma.o
/linux-master/arch/mips/jazz/
H A DMakefile6 obj-y := irq.o jazzdma.o reset.o setup.o
/linux-master/drivers/clk/stm32/
H A DMakefile1 obj-$(CONFIG_COMMON_CLK_STM32MP135) += clk-stm32mp13.o clk-stm32-core.o reset-stm32.o
2 obj-$(CONFIG_COMMON_CLK_STM32MP157) += clk-stm32mp1.o reset-stm32.o
/linux-master/drivers/power/reset/
H A Dat91-reset.c2 * Atmel AT91 SAM9 & SAMA5 SoCs reset code
20 #include <linux/reset-controller.h>
26 #include <dt-bindings/reset/sama7g5-reset.h>
47 * enum reset_type - reset types
48 * @RESET_TYPE_GENERAL: first power-up reset
51 * @RESET_TYPE_SOFTWARE: processor reset required by software
55 * @RESET_TYPE_ULP2: ULP2 reset
69 * struct at91_reset - AT91 reset specific data structure
70 * @rstc_base: base address for system reset
118 struct at91_reset *reset = container_of(this, struct at91_reset, nb); local
153 at91_reset_reason(struct at91_reset *reset) argument
195 struct at91_reset *reset = platform_get_drvdata(pdev); local
260 struct at91_reset *reset = to_at91_reset(rcdev); local
291 struct at91_reset *reset = to_at91_reset(rcdev); local
308 struct at91_reset *reset = to_at91_reset(rcdev); local
318 at91_rcdev_init(struct at91_reset *reset, struct platform_device *pdev) argument
343 struct at91_reset *reset; local
422 struct at91_reset *reset = platform_get_drvdata(pdev); local
[all...]
/linux-master/drivers/clk/actions/
H A Dowl-reset.c10 #include <linux/reset-controller.h>
12 #include "owl-reset.h"
17 struct owl_reset *reset = to_owl_reset(rcdev); local
18 const struct owl_reset_map *map = &reset->reset_map[id];
20 return regmap_update_bits(reset->regmap, map->reg, map->bit, 0);
26 struct owl_reset *reset = to_owl_reset(rcdev); local
27 const struct owl_reset_map *map = &reset->reset_map[id];
29 return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit);
45 struct owl_reset *reset = to_owl_reset(rcdev); local
46 const struct owl_reset_map *map = &reset
[all...]
/linux-master/drivers/clk/meson/
H A Dmeson-aoclk.h17 #include <linux/reset-controller.h>
25 const unsigned int *reset; member in struct:meson_aoclk_data
32 struct reset_controller_dev reset; member in struct:meson_aoclk_reset_controller
/linux-master/drivers/platform/mips/
H A DMakefile4 obj-$(CONFIG_LS2K_RESET) += ls2k-reset.o
/linux-master/drivers/clk/bcm/
H A Dclk-bcm2711-dvp.c7 #include <linux/reset-controller.h>
8 #include <linux/reset/reset-simple.h>
18 struct reset_simple_data reset; member in struct:clk_dvp
48 dvp->reset.rcdev.owner = THIS_MODULE;
49 dvp->reset.rcdev.nr_resets = NR_RESETS;
50 dvp->reset.rcdev.ops = &reset_simple_ops;
51 dvp->reset.rcdev.of_node = pdev->dev.of_node;
52 dvp->reset.membase = base + DVP_HT_RPI_SW_INIT;
53 spin_lock_init(&dvp->reset
[all...]
/linux-master/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_reset.h20 void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
/linux-master/include/linux/usb/
H A Dsl811.h23 void (*reset)(struct device *dev); member in struct:sl811_platform_data
/linux-master/drivers/clk/sunxi-ng/
H A Dccu-sun8i-r.h10 #include <dt-bindings/reset/sun8i-r-ccu.h>

Completed in 304 milliseconds

1234567891011>>