/linux-master/drivers/net/wireless/quantenna/qtnfmac/ |
H A D | qtn_hw_ids.h | 28 static inline unsigned int qtnf_chip_id_get(const void __iomem *regs_base) argument 30 u32 board_rev = readl(regs_base + QTN_REG_SYS_CTRL_CSR);
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/linux-master/drivers/clk/st/ |
H A D | clkgen.h | 44 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \ 47 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
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H A D | clkgen-fsyn.c | 237 * @regs_base: base address of the configuration registers. 244 void __iomem *regs_base; member in struct:st_clk_quadfs_pll 469 pll->regs_base = reg; 508 void __iomem *regs_base; member in struct:st_clk_quadfs_fsynth 907 fs->regs_base = reg;
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H A D | clkgen-pll.c | 202 * @regs_base: base of the PLL configuration register(s). 208 void __iomem *regs_base; member in struct:clkgen_pll 246 void __iomem *base = pll->regs_base; 665 pll->regs_base = reg;
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/linux-master/drivers/phy/samsung/ |
H A D | phy-exynos5-usbdrd.c | 749 void __iomem *regs_base = phy_drd->reg_phy; local 757 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 759 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 762 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 764 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 767 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 770 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 773 reg = readl(regs_base + EXYNOS850_DRD_HSP); 775 writel(reg, regs_base + EXYNOS850_DRD_HSP); 778 reg = readl(regs_base 830 void __iomem *regs_base = phy_drd->reg_phy; local [all...] |
/linux-master/arch/arm/include/asm/ |
H A D | kexec.h | 41 "stmia %[regs_base], {r0-r12}\n\t" 51 : [regs_base] "r" (&newregs->ARM_r0)
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/linux-master/drivers/spi/ |
H A D | spi-xilinx.c | 165 void __iomem *regs_base = xspi->regs; local 169 regs_base + XIPIF_V123B_RESETR_OFFSET); 174 regs_base + XIPIF_V123B_IIER_OFFSET); 176 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); 178 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); 183 regs_base + XSPI_CR_OFFSET); 510 void __iomem *regs_base = xspi->regs; local 515 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); 517 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
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/linux-master/drivers/net/ethernet/ezchip/ |
H A D | nps_enet.h | 155 * @regs_base: Base address of ENET memory-mapped control registers. 161 void __iomem *regs_base; member in struct:nps_enet_priv 178 iowrite32be(value, priv->regs_base + reg); 190 return ioread32be(priv->regs_base + reg);
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H A D | nps_enet.c | 44 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len); 57 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1); 388 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len); 595 priv->regs_base = devm_platform_ioremap_resource(pdev, 0); 596 if (IS_ERR(priv->regs_base)) { 597 err = PTR_ERR(priv->regs_base); 600 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
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/linux-master/drivers/media/platform/amphion/ |
H A D | vpu_windsor.h | 14 u32 regs_base, void __iomem *regs, u32 core_id);
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H A D | vpu_malone.h | 15 u32 regs_base, void __iomem *regs, u32 core_id);
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H A D | vpu_rpc.h | 57 u32 regs_base, void __iomem *regs, u32 index); 226 static inline int vpu_iface_config_system(struct vpu_core *core, u32 regs_base, void __iomem *regs) argument 233 ops->set_system_cfg(core->iface, regs_base, regs, core->id);
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/linux-master/drivers/video/fbdev/ |
H A D | tgafb.c | 639 void __iomem *regs_base; local 664 regs_base = par->tga_regs_base; 683 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG); 684 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG); 705 regs_base + TGA_MODE_REG); 716 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 735 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 767 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG); 783 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG); 797 __raw_writel(pixelmask, regs_base 937 void __iomem *regs_base; local [all...] |
/linux-master/drivers/dma/bestcomm/ |
H A D | gen_bd.c | 130 var->enable = bcom_eng->regs_base + 214 var->enable = bcom_eng->regs_base +
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H A D | fec.c | 123 var->enable = bcom_eng->regs_base + 224 var->enable = bcom_eng->regs_base +
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H A D | bestcomm.c | 421 bcom_eng->regs_base = res_bcom.start; 437 (long)bcom_eng->regs_base); 468 release_mem_region(bcom_eng->regs_base, sizeof(struct mpc52xx_sdma));
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H A D | ata.c | 79 var->enable = bcom_eng->regs_base +
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/linux-master/drivers/media/platform/samsung/s5p-mfc/ |
H A D | s5p_mfc_common.h | 102 #define mfc_read(dev, offset) readl(dev->regs_base + (offset)) 103 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ 263 * @regs_base: base address of the MFC hw registers 310 void __iomem *regs_base; member in struct:s5p_mfc_dev
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/linux-master/drivers/crypto/ |
H A D | sahara.c | 188 void __iomem *regs_base; member in struct:sahara_dev 224 writel(data, dev->regs_base + reg); 229 return readl(dev->regs_base + reg); 1296 dev->regs_base = devm_platform_ioremap_resource(pdev, 0); 1297 if (IS_ERR(dev->regs_base)) 1298 return PTR_ERR(dev->regs_base);
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/linux-master/include/linux/fsl/bestcomm/ |
H A D | bestcomm_priv.h | 71 phys_addr_t regs_base; member in struct:bcom_engine
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/linux-master/drivers/media/i2c/ccs/ |
H A D | ccs-data.c | 217 struct ccs_reg *regs_base = NULL, *regs = NULL; local 222 regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs); 312 if (!regs_base) 315 *__regs = regs_base;
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/linux-master/drivers/media/platform/rockchip/rkisp1/ |
H A D | rkisp1-debug.c | 124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers);
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H A D | rkisp1-resizer.c | 108 return rkisp1_read(rsz->rkisp1, rsz->regs_base + offset); 114 rkisp1_write(rsz->rkisp1, rsz->regs_base + offset, value); 693 rsz->regs_base = RKISP1_CIF_SRSZ_BASE; 696 rsz->regs_base = RKISP1_CIF_MRSZ_BASE;
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H A D | rkisp1-common.h | 397 * @regs_base: base register address offset 405 u32 regs_base; member in struct:rkisp1_resizer
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/linux-master/drivers/media/platform/chips-media/coda/ |
H A D | coda.h | 86 void __iomem *regs_base; member in struct:coda_dev
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