Searched refs:regs_base (Results 1 - 25 of 31) sorted by relevance

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/linux-master/drivers/net/wireless/quantenna/qtnfmac/
H A Dqtn_hw_ids.h28 static inline unsigned int qtnf_chip_id_get(const void __iomem *regs_base) argument
30 u32 board_rev = readl(regs_base + QTN_REG_SYS_CTRL_CSR);
/linux-master/drivers/clk/st/
H A Dclkgen.h44 #define CLKGEN_READ(pll, field) clkgen_read(pll->regs_base, \
47 #define CLKGEN_WRITE(pll, field, val) clkgen_write(pll->regs_base, \
H A Dclkgen-fsyn.c237 * @regs_base: base address of the configuration registers.
244 void __iomem *regs_base; member in struct:st_clk_quadfs_pll
469 pll->regs_base = reg;
508 void __iomem *regs_base; member in struct:st_clk_quadfs_fsynth
907 fs->regs_base = reg;
H A Dclkgen-pll.c202 * @regs_base: base of the PLL configuration register(s).
208 void __iomem *regs_base; member in struct:clkgen_pll
246 void __iomem *base = pll->regs_base;
665 pll->regs_base = reg;
/linux-master/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c749 void __iomem *regs_base = phy_drd->reg_phy; local
757 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL);
759 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL);
762 reg = readl(regs_base + EXYNOS850_DRD_CLKRST);
764 writel(reg, regs_base + EXYNOS850_DRD_CLKRST);
767 reg = readl(regs_base + EXYNOS850_DRD_UTMI);
770 writel(reg, regs_base + EXYNOS850_DRD_UTMI);
773 reg = readl(regs_base + EXYNOS850_DRD_HSP);
775 writel(reg, regs_base + EXYNOS850_DRD_HSP);
778 reg = readl(regs_base
830 void __iomem *regs_base = phy_drd->reg_phy; local
[all...]
/linux-master/arch/arm/include/asm/
H A Dkexec.h41 "stmia %[regs_base], {r0-r12}\n\t"
51 : [regs_base] "r" (&newregs->ARM_r0)
/linux-master/drivers/spi/
H A Dspi-xilinx.c165 void __iomem *regs_base = xspi->regs; local
169 regs_base + XIPIF_V123B_RESETR_OFFSET);
174 regs_base + XIPIF_V123B_IIER_OFFSET);
176 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
178 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
183 regs_base + XSPI_CR_OFFSET);
510 void __iomem *regs_base = xspi->regs; local
515 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
517 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
/linux-master/drivers/net/ethernet/ezchip/
H A Dnps_enet.h155 * @regs_base: Base address of ENET memory-mapped control registers.
161 void __iomem *regs_base; member in struct:nps_enet_priv
178 iowrite32be(value, priv->regs_base + reg);
190 return ioread32be(priv->regs_base + reg);
H A Dnps_enet.c44 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
57 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
388 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
595 priv->regs_base = devm_platform_ioremap_resource(pdev, 0);
596 if (IS_ERR(priv->regs_base)) {
597 err = PTR_ERR(priv->regs_base);
600 dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
/linux-master/drivers/media/platform/amphion/
H A Dvpu_windsor.h14 u32 regs_base, void __iomem *regs, u32 core_id);
H A Dvpu_malone.h15 u32 regs_base, void __iomem *regs, u32 core_id);
H A Dvpu_rpc.h57 u32 regs_base, void __iomem *regs, u32 index);
226 static inline int vpu_iface_config_system(struct vpu_core *core, u32 regs_base, void __iomem *regs) argument
233 ops->set_system_cfg(core->iface, regs_base, regs, core->id);
/linux-master/drivers/video/fbdev/
H A Dtgafb.c639 void __iomem *regs_base; local
664 regs_base = par->tga_regs_base;
683 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
684 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
705 regs_base + TGA_MODE_REG);
716 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
735 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
767 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
783 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
797 __raw_writel(pixelmask, regs_base
937 void __iomem *regs_base; local
[all...]
/linux-master/drivers/dma/bestcomm/
H A Dgen_bd.c130 var->enable = bcom_eng->regs_base +
214 var->enable = bcom_eng->regs_base +
H A Dfec.c123 var->enable = bcom_eng->regs_base +
224 var->enable = bcom_eng->regs_base +
H A Dbestcomm.c421 bcom_eng->regs_base = res_bcom.start;
437 (long)bcom_eng->regs_base);
468 release_mem_region(bcom_eng->regs_base, sizeof(struct mpc52xx_sdma));
H A Data.c79 var->enable = bcom_eng->regs_base +
/linux-master/drivers/media/platform/samsung/s5p-mfc/
H A Ds5p_mfc_common.h102 #define mfc_read(dev, offset) readl(dev->regs_base + (offset))
103 #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
263 * @regs_base: base address of the MFC hw registers
310 void __iomem *regs_base; member in struct:s5p_mfc_dev
/linux-master/drivers/crypto/
H A Dsahara.c188 void __iomem *regs_base; member in struct:sahara_dev
224 writel(data, dev->regs_base + reg);
229 return readl(dev->regs_base + reg);
1296 dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
1297 if (IS_ERR(dev->regs_base))
1298 return PTR_ERR(dev->regs_base);
/linux-master/include/linux/fsl/bestcomm/
H A Dbestcomm_priv.h71 phys_addr_t regs_base; member in struct:bcom_engine
/linux-master/drivers/media/i2c/ccs/
H A Dccs-data.c217 struct ccs_reg *regs_base = NULL, *regs = NULL; local
222 regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs);
312 if (!regs_base)
315 *__regs = regs_base;
/linux-master/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-debug.c124 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers);
H A Drkisp1-resizer.c108 return rkisp1_read(rsz->rkisp1, rsz->regs_base + offset);
114 rkisp1_write(rsz->rkisp1, rsz->regs_base + offset, value);
693 rsz->regs_base = RKISP1_CIF_SRSZ_BASE;
696 rsz->regs_base = RKISP1_CIF_MRSZ_BASE;
H A Drkisp1-common.h397 * @regs_base: base register address offset
405 u32 regs_base; member in struct:rkisp1_resizer
/linux-master/drivers/media/platform/chips-media/coda/
H A Dcoda.h86 void __iomem *regs_base; member in struct:coda_dev

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