/haiku/headers/private/graphics/radeon/ |
H A D | mmio.h | 14 #define INREG8( regs, addr ) (*(regs + (addr))) 16 #define OUTREG8( regs, addr, val ) do { *(regs + (addr)) = (val); } while( 0 ) 18 #define INREG( regs, addr ) (*((vuint32 *)(regs + (addr)))) 20 #define OUTREG( regs, addr, val ) do { *(vuint32 *)(regs + (addr)) = (val); } while( 0 ) 22 #define OUTREGP( regs, addr, val, mask ) \ 24 uint32 tmp = INREG( (regs), (add [all...] |
H A D | pll_access.h | 19 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ); 24 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ); 36 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ); 39 void Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ); 42 void Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask );
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/haiku/src/system/boot/platform/bios_ia32/ |
H A D | keyboard.cpp | 19 bios_regs regs; local 20 regs.eax = 0x0100; 21 call_bios(0x16, ®s); 24 if (regs.flags & ZERO_FLAG) 28 regs.eax = 0; 29 call_bios(0x16, ®s); 31 return regs.eax & 0xffff; 58 bios_regs regs; local 61 regs.eax = 0x0200; 62 call_bios(0x16, ®s); [all...] |
H A D | bios.cpp | 23 extern "C" void call_bios_internal(uint8 num, struct bios_regs* regs); 27 call_bios(uint8 num, struct bios_regs* regs) argument 34 num, regs->eax, regs->ebx, regs->ecx, regs->edx, regs->esi, regs->edi, 35 regs->es, regs [all...] |
H A D | apm.cpp | 28 struct bios_regs regs; local 29 regs.eax = BIOS_APM_CHECK; 30 regs.ebx = 0; 31 call_bios(0x15, ®s); 33 if ((regs.flags & CARRY_FLAG) != 0 34 || (regs.ebx & 0xffff) != 'PM') { 40 gKernelArgs.platform_args.apm.version = regs.eax & 0xffff; 41 gKernelArgs.platform_args.apm.flags = regs.ecx & 0xffff; 54 regs.eax = BIOS_APM_DISCONNECT; 55 regs [all...] |
/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | pll_access.c | 16 void RADEONPllErrataAfterIndex( vuint8 *regs, radeon_type asic ) argument 24 INREG( regs, RADEON_CLOCK_CNTL_DATA); 25 INREG( regs, RADEON_CRTC_GEN_CNTL); 28 void RADEONPllErrataAfterData( vuint8 *regs, radeon_type asic ) argument 50 save = INREG( regs, RADEON_CLOCK_CNTL_INDEX ); 52 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, tmp ); 53 tmp = INREG( regs, RADEON_CLOCK_CNTL_DATA ); 54 OUTREG( regs, RADEON_CLOCK_CNTL_INDEX, save ); 59 uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr ) argument 63 OUTREG8( regs, RADEON_CLOCK_CNTL_INDE 71 Radeon_OUTPLL( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val ) argument 84 Radeon_OUTPLLP( vuint8 *regs, radeon_type asic, uint8 addr, uint32 val, uint32 mask ) argument [all...] |
H A D | vip.c | 32 vuint8 *regs = di->regs; local 36 OUTREG( regs, RADEON_VIPH_REG_ADDR, (channel << 14) | address | 0x2000 ); 43 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, 0, 48 INREG( regs, RADEON_VIPH_REG_DATA ); 57 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, 62 *data = INREG( regs, RADEON_VIPH_REG_DATA ); 72 OUTREGP( regs, RADEON_VIPH_TIMEOUT_STAT, RADEON_VIPH_TIMEOUT_STAT_VIPH_REGR_DIS, 99 vuint8 *regs = di->regs; local 192 vuint8 *regs = di->regs; local 230 vuint8 *regs = di->regs; local 296 vuint8 *regs = di->regs; local 348 vuint8 *regs = di->regs; local 366 vuint8 *regs = di->regs; local [all...] |
H A D | CP_setup.c | 130 if( (INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_ACTIVE) == 0 ) { 147 INREG( di->regs, RADEON_RBBM_STATUS ), 148 INREG( di->regs, RADEON_CP_STAT ), 149 INREG( di->regs, RADEON_AIC_TLB_ADDR ), 150 INREG( di->regs, RADEON_AIC_TLB_DATA )); 167 int slots = INREG( di->regs, RADEON_RBBM_STATUS ) & RADEON_RBBM_FIFOCNT_MASK; 186 OUTREGP( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL, 192 if( (INREG( di->regs, RADEON_RB2D_DSTCACHE_CTLSTAT ) 208 vuint8 *regs = di->regs; local 326 vuint8 *regs = di->regs; local 377 vuint8 *regs = di->regs; local 393 vuint8 *regs = di->regs; local 434 vuint8 *regs = di->regs; local 582 vuint8 *regs = di->regs; local 642 vuint8 *regs = di->regs; local [all...] |
/haiku/src/system/libroot/os/arch/x86_64/ |
H A D | system_info.cpp | 16 __cpuid_count(eax, 0, info->regs.eax, info->regs.ebx, info->regs.ecx, 17 info->regs.edx);
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/haiku/src/add-ons/accelerants/radeon/ |
H A D | dpms.c | 59 vuint8 *regs = ai->regs; local 68 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON ); 70 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON ); 78 old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL); 82 Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb ); 84 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, 0, ~(RADEON_LVDS_BLON | RADEON_LVDS_ON) ); 87 Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl ); 97 vuint8 *regs = ai->regs; local 119 vuint8 *regs = ai->regs; local 150 vuint8 *regs = ai->regs; local 172 vuint8 *regs = ai->regs; local 198 vuint8 *regs = ai->regs; local 240 vuint8 *regs = ai->regs; local [all...] |
H A D | flat_panel.c | 23 vuint8 *regs = ai->regs; local 25 values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH ); 26 values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH ); 110 vuint8 *regs = ai->regs; local 112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch ); 113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch ); 120 vuint8 *regs = ai->regs; local 254 vuint8 *regs = ai->regs; local [all...] |
H A D | monitor_detection.c | 40 vuint8 *regs = info->ai->regs; local 43 value = INREG(regs, info->port); 56 vuint8 *regs = info->ai->regs; local 59 value = INREG(regs, info->port); 65 OUTREG(regs, info->port, value); 104 vuint8 *regs = ai->regs; local 109 old_crtc_ext_cntl = INREG(regs, RADEON_CRTC_EXT_CNT 180 vuint8 *regs = ai->regs; local 231 vuint8 *regs = ai->regs; local 334 vuint8 *regs = ai->regs; local 419 vuint8 *regs = ai->regs; local [all...] |
/haiku/src/add-ons/kernel/drivers/timer/ |
H A D | hpet.h | 23 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID) 24 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8) 25 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13) 26 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15) 27 #define HPET_GET_VENDOR_ID(regs) (((regs) [all...] |
/haiku/headers/private/kernel/arch/x86/ |
H A D | arch_hpet.h | 22 #define HPET_GET_REVID(regs) ((regs)->capabilities & HPET_CAP_MASK_REVID) 23 #define HPET_GET_NUM_TIMERS(regs) (((regs)->capabilities & HPET_CAP_MASK_NUMTIMERS) >> 8) 24 #define HPET_IS_64BIT(regs) (((regs)->capabilities & HPET_CAP_MASK_WIDTH) >> 13) 25 #define HPET_IS_LEGACY_CAPABLE(regs) (((regs)->capabilities & HPET_CAP_MASK_LEGACY) >> 15) 26 #define HPET_GET_VENDOR_ID(regs) (((regs) [all...] |
/haiku/src/system/kernel/arch/x86/64/ |
H A D | cpuid.cpp | 16 __cpuid_count(eax, ecx, info->regs.eax, info->regs.ebx, info->regs.ecx, 17 info->regs.edx);
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/haiku/src/system/kernel/arch/x86/32/ |
H A D | apm.cpp | 92 call_apm_bios(bios_regs *regs) argument 106 : "=a" (regs->eax), "=b" (regs->ebx), "=c" (regs->ecx), "=d" (regs->edx), 107 "=S" (regs->esi), "=m" (regs->flags) 108 : "a" (regs->eax), "b" (regs->ebx), "c" (regs 124 bios_regs regs; local 139 bios_regs regs; local 156 bios_regs regs; local 168 bios_regs regs; local 181 bios_regs regs; local 209 bios_regs regs; local [all...] |
/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_globals.h | 5 extern vuint32 *regs;
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H A D | mga_globals.c | 14 vuint32 *regs; variable
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/haiku/src/add-ons/accelerants/matrox/ |
H A D | global.h | 5 extern vuint32 *regs;
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/haiku/src/add-ons/accelerants/radeon_hd/ |
H A D | display.cpp | 40 /*! Populate regs with device dependant register locations */ 42 init_registers(register_info* regs, uint8 crtcID) argument 44 memset(regs, 0, sizeof(register_info)); 55 regs->vgaControl = AVIVO_D1VGA_CONTROL; 59 regs->vgaControl = AVIVO_D2VGA_CONTROL; 63 regs->vgaControl = EVERGREEN_D3VGA_CONTROL; 67 regs->vgaControl = EVERGREEN_D4VGA_CONTROL; 71 regs->vgaControl = EVERGREEN_D5VGA_CONTROL; 75 regs->vgaControl = EVERGREEN_D6VGA_CONTROL; 83 regs 597 register_info* regs = gDisplay[crtcID]->regs; local 662 register_info* regs = gDisplay[crtcID]->regs; local 698 register_info* regs = gDisplay[crtcID]->regs; local [all...] |
/haiku/src/add-ons/kernel/drivers/dvb/cx23882/ |
H A D | cx23882.h | 36 void * regs; member in struct:__anon4 55 #define reg_read8(offset) (*(volatile uint8 *) ((char *)(device->regs) + (offset))) 56 #define reg_read16(offset) (*(volatile uint16 *)((char *)(device->regs) + (offset))) 57 #define reg_read32(offset) (*(volatile uint32 *)((char *)(device->regs) + (offset))) 58 #define reg_write8(offset, value) (*(volatile uint8 *) ((char *)(device->regs) + (offset)) = value) 59 #define reg_write16(offset, value) (*(volatile uint16 *)((char *)(device->regs) + (offset)) = value) 60 #define reg_write32(offset, value) (*(volatile uint32 *)((char *)(device->regs) + (offset)) = value)
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/haiku/src/add-ons/kernel/drivers/graphics/vesa/ |
H A D | vesa.cpp | 133 bios_regs regs = {}; local 134 regs.eax = 0x4f01; 135 regs.ecx = mode; 136 regs.es = physicalAddress >> 4; 137 regs.edi = physicalAddress - (regs.es << 4); 139 status_t status = sBIOSModule->interrupt(state, 0x10, ®s); 146 if ((regs.eax & 0xffff) != 0x4f) { 148 "0x%04" B_PRIx32 "\n", mode, regs.eax & 0xffff); 160 bios_regs regs local 203 bios_regs regs = {}; local 233 bios_regs regs = {}; local 599 bios_regs regs = {}; local [all...] |
/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | globals.c | 15 vuint32 *regs; variable
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/haiku/headers/private/kernel/boot/ |
H A D | uart.h | 15 addr_range regs; member in struct:__anon9
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H A D | timer.h | 20 addr_range regs; member in struct:__anon2
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