Searched refs:regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX (Results 1 - 2 of 2) sorted by path

/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h1119 #define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 macro
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H A Dgc_11_0_3_offset.h1131 #define regSDMA1_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 macro
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