Searched refs:regSDMA0_QUEUE0_RB_CNTL (Results 1 - 5 of 5) sorted by path
/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_amdkfd_gfx_v11.c | 135 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; 139 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL; 146 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL); 358 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, 408 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, data); 427 for (reg = regSDMA0_QUEUE0_RB_CNTL; 480 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL); 547 temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL); 549 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, tem [all...] |
H A D | sdma_v6_0.c | 341 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 343 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 440 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); 448 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); 542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
|
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_11_0_0_offset.h | 190 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro [all...] |
H A D | gc_11_0_3_offset.h | 196 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro [all...] |
H A D | gc_11_5_0_offset.h | 195 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro [all...] |
Completed in 1014 milliseconds