Searched refs:regSDMA0_QUEUE0_RB_CNTL (Results 1 - 5 of 5) sorted by path

/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c135 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
139 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
146 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL);
358 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL,
408 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, data);
427 for (reg = regSDMA0_QUEUE0_RB_CNTL;
480 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
547 temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
549 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, tem
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H A Dsdma_v6_0.c341 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
343 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
440 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
448 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
542 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h190 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro
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H A Dgc_11_0_3_offset.h196 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro
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H A Dgc_11_5_0_offset.h195 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro
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