Searched refs:reg (Results 1 - 25 of 313) sorted by relevance

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/haiku/src/system/libroot/posix/glibc/include/arch/sparc/
H A Dsysdep.h25 #define SPARC_PIC_THUNK(reg) \
26 .ifndef __sparc_get_pc_thunk.reg; \
27 .section .text.__sparc_get_pc_thunk.reg,"axG",@progbits,__sparc_get_pc_thunk.reg,comdat; \
29 .weak __sparc_get_pc_thunk.reg; \
30 .hidden __sparc_get_pc_thunk.reg; \
31 .type __sparc_get_pc_thunk.reg, #function; \
32 __sparc_get_pc_thunk.reg: \
34 add %o7, %reg, %##reg; \
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/haiku/src/system/kernel/arch/generic/
H A Ddebug_uart.cpp11 DebugUART::Out8(int reg, uint8 value) argument
15 *((uint8 *)Base() + reg * sizeof(uint32)) = value;
18 if ((Base() + reg) <= 0xFFFF)
19 __asm__ volatile ("outb %%al,%%dx" : : "a" (value), "d" (Base() + reg));
21 *((uint8 *)Base() + reg) = value;
23 *((uint8 *)Base() + reg) = value;
29 DebugUART::In8(int reg) argument
33 return *((uint8 *)Base() + reg * sizeof(uint32));
36 if ((Base() + reg) <= 0xFFFF) {
38 __asm__ volatile ("inb %%dx,%%al" : "=a" (_v) : "d" (Base() + reg));
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/haiku/src/system/libroot/posix/glibc/include/
H A Dsysdep.h42 # define cfi_def_cfa(reg, off) .cfi_def_cfa reg, off
43 # define cfi_def_cfa_register(reg) .cfi_def_cfa_register reg
46 # define cfi_offset(reg, off) .cfi_offset reg, off
47 # define cfi_rel_offset(reg, off) .cfi_rel_offset reg, off
49 # define cfi_return_column(reg) .cfi_return_column reg
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/haiku/src/add-ons/accelerants/3dfx/
H A D3dfx_edid.cpp23 uint32 reg = INREG32(VIDEO_SERIAL_PARALLEL_PORT); local
24 *_clock = (reg & VSP_SCL0_IN) ? 1 : 0;;
25 *data = (reg & VSP_SDA0_IN) ? 1 : 0;
35 uint32 reg = (INREG32(VIDEO_SERIAL_PARALLEL_PORT) local
37 reg = (reg | (_clock ? VSP_SCL0_OUT : 0) | (data ? VSP_SDA0_OUT : 0));
38 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg);
56 uint32 reg = INREG32(VIDEO_SERIAL_PARALLEL_PORT); local
57 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg | VSP_ENABLE_IIC0);
61 OUTREG32(VIDEO_SERIAL_PARALLEL_PORT, reg);
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/haiku/src/add-ons/kernel/drivers/network/wlan/realtekwifi/dev/rtwn/
H A Dif_rtwn_efuse.c57 uint32_t reg; local
64 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
65 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
67 reg | R92C_SYS_FUNC_EN_ELDR);
71 reg = rtwn_read_2(sc, R92C_SYS_CLKR);
72 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
75 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
86 uint32_t reg; local
92 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
93 reg
123 uint8_t reg; local
179 uint8_t msk, off, reg; local
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/haiku/src/add-ons/kernel/drivers/network/ether/vt612x/dev/vge/
H A Dif_vgevar.h217 #define CSR_WRITE_STREAM_4(sc, reg, val) \
218 bus_write_stream_4(sc->vge_res, reg, val)
219 #define CSR_WRITE_4(sc, reg, val) \
220 bus_write_4(sc->vge_res, reg, val)
221 #define CSR_WRITE_2(sc, reg, val) \
222 bus_write_2(sc->vge_res, reg, val)
223 #define CSR_WRITE_1(sc, reg, val) \
224 bus_write_1(sc->vge_res, reg, val)
226 #define CSR_READ_4(sc, reg) \
227 bus_read_4(sc->vge_res, reg)
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/haiku/src/add-ons/kernel/drivers/network/ether/ipro1000/dev/e1000/
H A De1000_osdep.c45 e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) argument
47 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2);
51 e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value) argument
53 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);
74 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) argument
80 *value = pci_read_config(dev, offset + reg, 2);
88 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) argument
94 pci_write_config(dev, offset + reg, *value, 2);
H A De1000_osdep.h179 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \
180 ? reg : e1000_translate_register_82542(reg))
196 #define E1000_READ_REG(hw, reg) \
199 E1000_REGISTER(hw, reg))
201 #define E1000_WRITE_REG(hw, reg, value) \
204 E1000_REGISTER(hw, reg), value)
206 #define E1000_READ_REG_ARRAY(hw, reg, index) \
209 E1000_REGISTER(hw, reg) + ((index)<< 2))
211 #define E1000_WRITE_REG_ARRAY(hw, reg, inde
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/haiku/src/system/kernel/arch/arm/
H A Darch_uart_8250_omap.cpp10 #include <arch/arm/reg.h>
48 ArchUART8250Omap::Out8(int reg, uint8 value) argument
50 *((uint8 *)Base() + reg * sizeof(uint32)) = value;
55 ArchUART8250Omap::In8(int reg) argument
57 return *((uint8 *)Base() + reg * sizeof(uint32));
/haiku/src/kits/debugger/dwarf/
H A DCfaRule.h50 inline void SetToRegister(uint32 reg);
75 { return fRegisterOffset.reg; }
79 inline void SetToRegisterOffset(uint32 reg, uint64 offset);
82 inline void SetRegister(uint32 reg);
90 uint32 reg; member in struct:CfaCfaRule::__anon37::__anon38
138 CfaRule::SetToRegister(uint32 reg) argument
141 fRegister = reg;
181 CfaCfaRule::SetToRegisterOffset(uint32 reg, uint64 offset) argument
184 fRegisterOffset.reg = reg;
199 SetRegister(uint32 reg) argument
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H A DCfaContext.cpp112 CfaContext::SetReturnAddressRegister(uint32 reg) argument
114 fReturnAddressRegister = reg;
119 CfaContext::RestoreRegisterRule(uint32 reg) argument
121 if (CfaRule* rule = RegisterRule(reg)) {
123 *rule = *fInitialRuleSet->RegisterRule(reg);
/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/mii/
H A De1000phy.c189 uint16_t reg, page; local
191 reg = PHY_READ(sc, E1000_SCR);
193 reg &= ~E1000_SCR_AUTO_X_MODE;
194 PHY_WRITE(sc, E1000_SCR, reg);
199 reg = PHY_READ(sc, E1000_SCR);
200 reg &= ~E1000_SCR_MODE_MASK;
201 reg |= E1000_SCR_MODE_1000BX;
202 PHY_WRITE(sc, E1000_SCR, reg);
206 reg = PHY_READ(sc, E1000_SCR);
207 reg |
311 int reg; local
477 uint16_t reg; local
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/haiku/src/add-ons/kernel/drivers/network/ether/syskonnect/dev/mii/
H A De1000phy.c189 uint16_t reg, page; local
191 reg = PHY_READ(sc, E1000_SCR);
193 reg &= ~E1000_SCR_AUTO_X_MODE;
194 PHY_WRITE(sc, E1000_SCR, reg);
199 reg = PHY_READ(sc, E1000_SCR);
200 reg &= ~E1000_SCR_MODE_MASK;
201 reg |= E1000_SCR_MODE_1000BX;
202 PHY_WRITE(sc, E1000_SCR, reg);
206 reg = PHY_READ(sc, E1000_SCR);
207 reg |
311 int reg; local
477 uint16_t reg; local
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/haiku/src/add-ons/kernel/drivers/network/wlan/atheroswifi/dev/ath/
H A Dah_osdep.c150 ath_hal_reg_whilst_asleep(struct ath_hal *ah, uint32_t reg) argument
153 if (reg >= 0x4000 && reg < 0x5000)
155 if (reg >= 0x6000 && reg < 0x7000)
157 if (reg >= 0x7000 && reg < 0x8000)
260 r->reg = 0;
274 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) argument
281 if (! ath_hal_reg_whilst_asleep(ah, reg)
308 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) argument
372 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) argument
395 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) argument
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/haiku/src/add-ons/kernel/drivers/audio/hda/
H A Ddriver.h88 uint8 Read8(uint32 reg) argument
90 return *(regs + reg);
93 uint16 Read16(uint32 reg) argument
95 return *(vuint16*)(regs + reg);
98 uint32 Read32(uint32 reg) argument
100 return *(vuint32*)(regs + reg);
103 void Write8(uint32 reg, uint8 value) argument
105 *(regs + reg) = value;
108 void Write16(uint32 reg, uint16 value) argument
110 *(vuint16*)(regs + reg)
113 Write32(uint32 reg, uint32 value) argument
118 ReadModifyWrite8(uint32 reg, uint8 mask, uint8 value) argument
126 ReadModifyWrite16(uint32 reg, uint16 mask, uint16 value) argument
134 ReadModifyWrite32(uint32 reg, uint32 mask, uint32 value) argument
186 Read8(uint32 reg) argument
191 Read16(uint32 reg) argument
196 Read32(uint32 reg) argument
201 Write8(uint32 reg, uint8 value) argument
206 Write16(uint32 reg, uint16 value) argument
211 Write32(uint32 reg, uint32 value) argument
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/haiku/src/libs/compat/freebsd_network/
H A Dmii.c19 __haiku_miibus_readreg(device_t device, int phy, int reg) argument
24 return device->methods.miibus_readreg(device, phy, reg);
29 __haiku_miibus_writereg(device_t device, int phy, int reg, int data) argument
34 return device->methods.miibus_writereg(device, phy, reg, data);
/haiku/src/add-ons/kernel/drivers/network/ether/intel22x/dev/igc/
H A Digc_osdep.h79 #define IGC_REGISTER(hw, reg) reg
95 #define IGC_READ_REG(hw, reg) \
98 IGC_REGISTER(hw, reg))
100 #define IGC_WRITE_REG(hw, reg, value) \
103 IGC_REGISTER(hw, reg), value)
105 #define IGC_READ_REG_ARRAY(hw, reg, index) \
108 IGC_REGISTER(hw, reg) + ((index)<< 2))
110 #define IGC_WRITE_REG_ARRAY(hw, reg, index, value) \
113 IGC_REGISTER(hw, reg)
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/haiku/src/libs/compat/freebsd_network/compat/dev/mii/
H A Dmii_bitbang.h51 int phy, int reg);
54 int phy, int reg, int val);
/haiku/src/add-ons/kernel/drivers/audio/ac97/geode/
H A Ddriver.h68 uint8 Read8(uint32 reg) argument
70 return gPci->read_io_8(nabmbar + reg);
73 uint16 Read16(uint32 reg) argument
75 return gPci->read_io_16(nabmbar + reg);
78 uint32 Read32(uint32 reg) argument
80 return gPci->read_io_32(nabmbar + reg);
83 void Write8(uint32 reg, uint8 value) argument
85 gPci->write_io_8(nabmbar + reg, value);
88 void Write16(uint32 reg, uint16 value) argument
90 gPci->write_io_16(nabmbar + reg, valu
93 Write32(uint32 reg, uint32 value) argument
135 Read8(uint32 reg) argument
140 Read16(uint32 reg) argument
145 Read32(uint32 reg) argument
150 Write8(uint32 reg, uint8 value) argument
155 Write16(uint32 reg, uint16 value) argument
160 Write32(uint32 reg, uint32 value) argument
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/haiku/src/add-ons/accelerants/s3/
H A Dvirge_edid.cpp56 uint8 reg = ReadReg8(DDC_REG); local
58 *_clock = (reg & 0x4) != 0;
59 *data = (reg & 0x8) != 0;
69 uint8 reg = 0x10; local
72 reg |= 0x1;
74 reg |= 0x2;
76 WriteReg8(DDC_REG, reg);
/haiku/src/add-ons/kernel/drivers/audio/ac97/sis7018/
H A DMixer.h42 bool _WaitPortReady(uint8 reg, uint32 mask, uint32* result = NULL);
44 uint16 _ReadAC97(uint8 reg);
45 void _WriteAC97(uint8 reg, uint16 date);
46 static uint16 _ReadAC97(void* cookie, uint8 reg);
47 static void _WriteAC97(void* cookie, uint8 reg, uint16 data);
/haiku/src/add-ons/kernel/drivers/network/ether/ipro100/dev/fxp/
H A Dif_fxpvar.h249 #define CSR_READ_1(sc, reg) bus_read_1(sc->fxp_res[0], reg)
250 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg)
251 #define CSR_READ_4(sc, reg) bus_read_4(sc->fxp_res[0], reg)
252 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val)
253 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, va
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/haiku/src/libs/compat/openbsd_network/compat/dev/pci/
H A Dpcivar.h28 #define pci_conf_read(pct, pcitag, reg) \
29 pci_read_config(SC_DEV_FOR_PCI, reg, sizeof(pcireg_t))
30 #define pci_conf_write(pct, pcitag, reg, val) \
31 pci_write_config(SC_DEV_FOR_PCI, reg, val, sizeof(pcireg_t))
34 #define pci_mapreg_type(pct, pcitag, reg) \
35 pci_mapreg_type_openbsd(SC_DEV_FOR_PCI, reg)
36 #define pci_mapreg_map(pa, reg, type, flags, tagp, handlep, basep, sizep, maxsize) \
37 pci_mapreg_map_openbsd(SC_DEV_FOR_PCI, reg, type, flags, tagp, handlep, basep, sizep, maxsize)
56 pci_mapreg_type_openbsd(device_t dev, int reg) argument
58 return (_PCI_MAPREG_TYPEBITS(pci_read_config(dev, reg, sizeo
62 pci_mapreg_map_openbsd(device_t dev, int reg, pcireg_t type, int flags, bus_space_tag_t* tagp, bus_space_handle_t* handlep, bus_addr_t* basep, bus_size_t* sizep, bus_size_t maxsize) argument
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/haiku/src/add-ons/accelerants/radeon_hd/
H A Dbios.cpp68 uint32 reg; local
72 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
76 if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
80 reg = Read32(OUT, EVERGREEN_CRTC_CONTROL
92 if ((reg & EVERGREEN_CRTC_MASTER_EN) != 0)
96 reg = Read32(OUT, AVIVO_D1CRTC_CONTROL)
98 if ((reg & AVIVO_CRTC_EN) != 0) {
103 reg = Read32(OUT, RADEON_CRTC_GEN_CNTL)
105 if ((reg & RADEON_CRTC_EN) != 0)
111 reg
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/haiku/headers/private/debugger/arch/
H A DCpuState.h35 virtual bool GetRegisterValue(const Register* reg,
37 virtual bool SetRegisterValue(const Register* reg,

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