/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | mmc_core.c | 237 u32 value = readl(mmcaddr + MMC_CNTRL); 262 mmc->mmc_tx_octetcount_gb += readl(mmcaddr + MMC_TX_OCTETCOUNT_GB); 263 mmc->mmc_tx_framecount_gb += readl(mmcaddr + MMC_TX_FRAMECOUNT_GB); 264 mmc->mmc_tx_broadcastframe_g += readl(mmcaddr + 266 mmc->mmc_tx_multicastframe_g += readl(mmcaddr + 268 mmc->mmc_tx_64_octets_gb += readl(mmcaddr + MMC_TX_64_OCTETS_GB); 270 readl(mmcaddr + MMC_TX_65_TO_127_OCTETS_GB); 272 readl(mmcaddr + MMC_TX_128_TO_255_OCTETS_GB); 274 readl(mmcaddr + MMC_TX_256_TO_511_OCTETS_GB); 276 readl(mmcadd [all...] |
H A D | dwmac4_dma.c | 20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 81 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, chan)); 102 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, chan)); 126 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 144 value = readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, chan)); 158 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); 176 value = readl(ioaddr + DMA_BUS_MODE); 201 readl(ioaddr + DMA_CHAN_CONTROL(dwmac4_addrs, channel)); 203 readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel)); 205 readl(ioadd [all...] |
/linux-master/sound/soc/sunxi/ |
H A D | sun8i-adda-pr-regmap.c | 35 writel(readl(base) | ADDA_PR_RESET, base); 38 writel(readl(base) & ~ADDA_PR_WRITE, base); 41 tmp = readl(base); 47 *val = readl(base) & ADDA_PR_DATA_OUT_MASK; 58 writel(readl(base) | ADDA_PR_RESET, base); 61 tmp = readl(base); 67 tmp = readl(base); 73 writel(readl(base) | ADDA_PR_WRITE, base); 76 writel(readl(base) & ~ADDA_PR_WRITE, base);
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/linux-master/drivers/clk/mediatek/ |
H A D | clk-fhctl.c | 59 readl(regs->reg_hp_en), readl(regs->reg_clk_con), 60 readl(regs->reg_slope0), readl(regs->reg_slope1)); 62 readl(regs->reg_cfg), readl(regs->reg_updnlmt), 63 readl(regs->reg_dds), readl(regs->reg_dvfs), 64 readl(regs->reg_mon)); 65 pr_info("pcw<%x>\n", readl(pl [all...] |
/linux-master/drivers/media/platform/samsung/s5p-jpeg/ |
H A D | jpeg-hw-s5p.c | 22 reg = readl(regs + S5P_JPG_SW_RESET); 26 reg = readl(regs + S5P_JPG_SW_RESET); 45 reg = readl(regs + S5P_JPGCMOD); 59 reg = readl(regs + S5P_JPGMOD); 74 reg = readl(regs + S5P_JPGMOD); 82 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK; 89 reg = readl(regs + S5P_JPGDRI_U); 94 reg = readl(regs + S5P_JPGDRI_L); 104 reg = readl(regs + S5P_JPG_QTBL); 114 reg = readl(reg [all...] |
H A D | jpeg-hw-exynos4.c | 20 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 24 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 36 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); 67 reg = readl(base + EXYNOS4_IMG_FMT_REG) & 141 reg = readl(base + EXYNOS4_IMG_FMT_REG) & 174 reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; 177 reg = readl(base + EXYNOS4_INT_EN_REG) & 185 return readl(base + EXYNOS4_INT_STATUS_REG); 190 return readl(base + EXYNOS4_FIFO_STATUS_REG); 197 reg = readl(bas [all...] |
/linux-master/drivers/net/ethernet/intel/i40e/ |
H A D | i40e_io.h | 11 #define rd32(a, reg) readl((a)->hw_addr + (reg)) 14 #define i40e_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT)
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/linux-master/arch/arm/mach-clps711x/ |
H A D | board-dt.c | 48 id[0] = readl(CLPS711X_VIRT_BASE + UNIQID); 49 id[1] = readl(CLPS711X_VIRT_BASE + RANDID0); 50 id[2] = readl(CLPS711X_VIRT_BASE + RANDID1); 51 id[3] = readl(CLPS711X_VIRT_BASE + RANDID2); 52 id[4] = readl(CLPS711X_VIRT_BASE + RANDID3); 53 system_rev = SYSFLG1_VERID(readl(CLPS711X_VIRT_BASE + SYSFLG1));
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/linux-master/sound/arm/ |
H A D | pxa2xx-ac97-lib.c | 68 val = (readl(reg_addr) & 0xffff); 71 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1) <= 0 && 72 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE)) { 74 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits); 82 val = (readl(reg_addr) & 0xffff); 84 wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_SDONE, 1); 110 if (wait_event_timeout(gsr_wq, (readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE, 1) <= 0 && 111 !((readl(ac97_reg_base + GSR) | gsr_bits) & GSR_CDONE)) { 113 __func__, reg, readl(ac97_reg_base + GSR) | gsr_bits); 127 writel(readl(ac97_reg_bas [all...] |
/linux-master/arch/arm/mach-dove/ |
H A D | mpp.c | 60 readl(DOVE_MPP_CTRL4_VIRT_BASE)); 63 readl(DOVE_PMU_MPP_GENERAL_CTRL)); 65 pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE)); 70 u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE); 81 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 82 u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1); 83 u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE); 84 u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2); 121 u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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/linux-master/arch/arm/mach-s3c/ |
H A D | setup-usb-phy-s3c64xx.c | 28 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); 31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; 54 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); 68 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | 71 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS);
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/linux-master/drivers/phy/mediatek/ |
H A D | phy-mtk-io.h | 16 u32 tmp = readl(reg); 24 u32 tmp = readl(reg); 32 u32 tmp = readl(reg);
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/linux-master/drivers/misc/ibmasm/ |
H A D | lowlevel.h | 43 return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); 48 return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER); 54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); 60 writel( readl(ctrl_reg) | mask, ctrl_reg); 91 mfa = readl(base_address + OUTBOUND_QUEUE_PORT); 105 u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
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/linux-master/drivers/clk/ingenic/ |
H A D | pm.c | 20 u32 val = readl(ingenic_cgu_base + CGU_REG_LCR); 29 u32 val = readl(ingenic_cgu_base + CGU_REG_LCR);
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/linux-master/drivers/net/ethernet/samsung/sxgbe/ |
H A D | sxgbe_core.c | 26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); 34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); 54 lpi_status = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); 74 irq_status = readl(ioaddr + SXGBE_CORE_INT_STATUS_REG); 106 high_word = readl(ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); 107 low_word = readl(ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); 122 tx_config = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); 134 rx_config = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); 144 return readl(ioaddr + SXGBE_CORE_VERSION_REG); 151 return readl(ioadd [all...] |
/linux-master/drivers/clk/mvebu/ |
H A D | orion.c | 30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & 47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & 62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & 100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & 115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & 130 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & 174 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & 187 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & 225 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & 240 u32 opt = (readl(sa [all...] |
/linux-master/drivers/media/platform/samsung/exynos4-is/ |
H A D | fimc-lite-reg.c | 25 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); 30 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); 42 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS); 49 u32 intsrc = readl(dev->regs + FLITE_REG_CISTATUS); 56 u32 cfg = readl(dev->regs + FLITE_REG_CISTATUS2); 77 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); 85 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); 92 u32 cfg = readl(dev->regs + FLITE_REG_CIIMGCPT); 103 u32 cfg = readl(dev->regs + FLITE_REG_CIGCTRL); 144 cfg = readl(de [all...] |
/linux-master/drivers/net/ethernet/sunplus/ |
H A D | spl2sw_mac.c | 26 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); 32 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); 42 reg = readl(comm->l2sw_reg_base + L2SW_CPU_CNTL); 48 reg = readl(comm->l2sw_reg_base + L2SW_PORT_CNTL0); 72 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, 80 readl(comm->l2sw_reg_base + L2SW_WT_MAC_AD0), 82 readl(comm->l2sw_reg_base + L2SW_W_MAC_47_16)), 84 readl(comm->l2sw_reg_base + L2SW_W_MAC_15_0))); 108 ret = read_poll_timeout(readl, reg, reg & MAC_W_MAC_DONE, 1, 200, true, 116 readl(com [all...] |
/linux-master/sound/soc/pxa/ |
H A D | pxa2xx-i2s.c | 115 readl(i2s_reg_base + SADR); 177 writel(readl(i2s_reg_base + SACR0) | (SACR0_BCKD), i2s_reg_base + SACR0); 179 writel(readl(i2s_reg_base + SACR0) | (SACR0_RFTH(14) | SACR0_TFTH(1)), i2s_reg_base + SACR0); 180 writel(readl(i2s_reg_base + SACR1) | (pxa_i2s.fmt), i2s_reg_base + SACR1); 183 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_TFS), i2s_reg_base + SAIMR); 185 writel(readl(i2s_reg_base + SAIMR) | (SAIMR_RFS), i2s_reg_base + SAIMR); 222 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DRPL), i2s_reg_base + SACR1); 224 writel(readl(i2s_reg_base + SACR1) & (~SACR1_DREC), i2s_reg_base + SACR1); 225 writel(readl(i2s_reg_base + SACR0) | (SACR0_ENB), i2s_reg_base + SACR0); 244 writel(readl(i2s_reg_bas [all...] |
/linux-master/sound/soc/amd/rpl/ |
H A D | rpl_acp6x.h | 30 return readl(base_addr - ACP6x_PHY_BASE_ADDRESS);
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/linux-master/arch/arm/plat-orion/ |
H A D | time.c | 67 return ~readl(timer_base + TIMER0_VAL_OFF); 89 u = readl(bridge_base + BRIDGE_MASK_OFF); 101 u = readl(timer_base + TIMER_CTRL_OFF); 118 u = readl(timer_base + TIMER_CTRL_OFF); 122 u = readl(bridge_base + BRIDGE_MASK_OFF); 145 u = readl(bridge_base + BRIDGE_MASK_OFF); 149 u = readl(timer_base + TIMER_CTRL_OFF); 188 return ~readl(timer_base + TIMER0_VAL_OFF); 223 u = readl(bridge_base + BRIDGE_MASK_OFF); 225 u = readl(timer_bas [all...] |
/linux-master/drivers/ata/ |
H A D | ahci_xgene.c | 93 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */ 95 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) { 160 fbs = readl(port_mmio + PORT_FBS); 162 fbs = readl(port_mmio + PORT_FBS); 200 port_fbs = readl(port_mmio + PORT_FBS); 223 return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 && 224 readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF); 271 val = readl(mmio + PORTCFG); 274 readl(mmio + PORTCFG); /* Force a barrier */ 277 readl(mmi [all...] |
/linux-master/drivers/cache/ |
H A D | sifive_ccache.c | 109 cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); 116 cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); 173 return readl(ccache_base + SIFIVE_CCACHE_WAYENABLE) & 0xFF; 209 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_HIGH); 210 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_LOW); 213 readl(ccache_base + SIFIVE_CCACHE_DIRECCFIX_COUNT); 219 add_h = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_HIGH); 220 add_l = readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_LOW); 222 readl(ccache_base + SIFIVE_CCACHE_DIRECCFAIL_COUNT); 229 add_h = readl(ccache_bas [all...] |
/linux-master/drivers/scsi/bfa/ |
H A D | bfa_ioc_ct.c | 60 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); 67 readl(ioc->ioc_regs.ioc_usage_sem_reg); 74 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); 87 readl(ioc->ioc_regs.ioc_usage_sem_reg); 98 readl(ioc->ioc_regs.ioc_usage_sem_reg); 113 usecnt = readl(ioc->ioc_regs.ioc_usage_reg); 120 readl(ioc->ioc_regs.ioc_usage_sem_reg); 134 readl(ioc->ioc_regs.ll_halt); 135 readl(ioc->ioc_regs.alt_ll_halt); 138 readl(io [all...] |
/linux-master/drivers/power/reset/ |
H A D | gemini-poweroff.c | 42 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 46 val = readl(gpw->base + GEMINI_PWC_STATREG); 79 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 112 val = readl(gpw->base + GEMINI_PWC_IDREG); 126 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 131 val = readl(gpw->base + GEMINI_PWC_CTRLREG); 136 val = readl(gpw->base + GEMINI_PWC_STATREG); 138 val = readl(gpw->base + GEMINI_PWC_STATREG); 141 val = readl(gpw->base + GEMINI_PWC_CTRLREG);
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