Searched refs:pxlclk (Results 1 - 8 of 8) sorted by relevance

/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c50 u64 pxlclk, aclk; local
57 pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL;
60 kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk);
150 err = clk_set_rate(master->pxlclk, mode->crtc_clock * 1000);
152 DRM_ERROR("failed to set pxlclk for pipe%d\n", master->id);
153 err = clk_prepare_enable(master->pxlclk);
189 clk_disable_unprepare(master->pxlclk);
404 unsigned long pxlclk)
407 * the aclk needs run on the double rate of pxlclk
410 return pxlclk *
403 komeda_calc_min_aclk_rate(struct komeda_crtc *kcrtc, unsigned long pxlclk) argument
420 unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000; local
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H A Dkomeda_pipeline.c58 clk_put(pipe->pxlclk);
H A Dkomeda_dev.c122 pipe->pxlclk = clk;
H A Dkomeda_pipeline.h392 /** @pxlclk: pixel clock */
393 struct clk *pxlclk; member in struct:komeda_pipeline
/linux-master/drivers/gpu/drm/arm/
H A Dmalidp_crtc.c38 rate = clk_round_rate(hwdev->pxlclk, req_rate);
40 DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
63 clk_prepare_enable(hwdev->pxlclk);
66 clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
88 clk_disable_unprepare(hwdev->pxlclk);
H A Dmalidp_hw.h240 struct clk *pxlclk; member in struct:malidp_hw_device
H A Dmalidp_drv.c744 hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
745 if (IS_ERR(hwdev->pxlclk))
746 return PTR_ERR(hwdev->pxlclk);
H A Dmalidp_hw.c484 unsigned long pxlclk = vm->pixelclock; /* Hz */ local
492 * mclk = max(a, 1.5) * pxlclk
502 mclk = a * pxlclk / 10;
825 unsigned long pxlclk = vm->pixelclock; local
840 /* mclk can't be slower than pxlclk. */
843 mclk = (pxlclk * numerator) / denominator;

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