Searched refs:pll_readl (Results 1 - 2 of 2) sorted by path

/linux-master/drivers/clk/pistachio/
H A Dclk-pll.c78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) function
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))
110 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD;
119 val = pll_readl(pll, PLL_CTRL3);
162 val = pll_readl(pll, PLL_CTRL3);
167 val = pll_readl(pll, PLL_CTRL4);
181 val = pll_readl(pll, PLL_CTRL3);
190 return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);
226 val = pll_readl(pll, PLL_CTRL1);
233 val = pll_readl(pl
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/linux-master/drivers/clk/tegra/
H A Dclk-pll.c230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset) macro
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
362 val = pll_readl(pll->params->iddq_reg, pll);
369 val = pll_readl(pll->params->reset_reg, pll);
407 val = pll_readl(pll->params->reset_reg, pll);
413 val = pll_readl(pll->params->iddq_reg, pll);
423 u32 val = pll_readl(pl
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