Searched refs:pll_mul (Results 1 - 5 of 5) sorted by relevance

/linux-master/arch/mips/include/asm/octeon/
H A Dcvmx-dbg-defs.h51 uint64_t pll_mul:3; member in struct:cvmx_dbg_data::cvmx_dbg_data_cn30xx
61 uint64_t pll_mul:3;
/linux-master/drivers/media/i2c/
H A Dov8865.c491 * +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
522 unsigned int pll_mul; member in struct:ov8865_pll1_config
539 * +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
565 unsigned int pll_mul; member in struct:ov8865_pll2_config
719 .pll_mul = 75,
730 .pll_mul = 30,
746 .pll_mul = 75,
755 .pll_mul = 30,
769 .pll_mul = 75,
778 .pll_mul
[all...]
H A Dov5648.c517 * +-+ pll_mul (0x3036 [7:0])
544 unsigned int pll_mul; member in struct:ov5648_pll1_config
673 .pll_mul = 84,
687 .pll_mul = 105,
1227 pll1_rate = xvclk_rate * config->pll_mul;
1280 OV5648_PLL_MUL(config->pll_mul));
H A Dtc358746.c162 u16 pll_mul; member in struct:tc358746
388 u16 mul = tc358746->pll_mul;
874 tc358746->pll_mul = m_best;
/linux-master/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h1389 * @pll_mul: main clock PLL multiplier hardware limit
1407 u64 pll_mul : 3; member in struct:fus_dat1::__anon138
1433 u64 pll_mul : 3;

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