Searched refs:pll_info (Results 1 - 23 of 23) sorted by relevance

/haiku/src/tests/add-ons/accelerants/intel_extreme/
H A DPllTest.cpp90 gInfo->shared_info->pll_info.reference_frequency = 120000;
91 gInfo->shared_info->pll_info.max_frequency = 350000;
92 gInfo->shared_info->pll_info.min_frequency = 20000;
96 gInfo->shared_info->pll_info.reference_frequency = 96000;
97 gInfo->shared_info->pll_info.max_frequency = 400000;
98 gInfo->shared_info->pll_info.min_frequency = 20000;
101 gInfo->shared_info->pll_info.reference_frequency = 96000;
102 gInfo->shared_info->pll_info.max_frequency = 400000;
103 gInfo->shared_info->pll_info.min_frequency = 20000;
113 gInfo->shared_info->pll_info
[all...]
/haiku/src/add-ons/accelerants/radeon_hd/
H A Dpll.h48 struct pll_info { struct
108 status_t pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID);
113 status_t pll_compute(pll_info* pll);
114 void pll_setup_flags(pll_info* pll, uint8 crtcID);
115 status_t pll_limit_probe(pll_info* pll);
116 status_t pll_ppll_ss_probe(pll_info* pll, uint32 ssID);
117 status_t pll_asic_ss_probe(pll_info* pll, uint32 ssID);
H A Ddisplay.h24 void display_crtc_ss(pll_info* pll, int command);
H A Dpll.cpp52 * The reference clock signal frequency is pll_info::referenceFreq (in kHz).
54 * (1) divided by the (integer) reference divider (pll_info::referenceDiv).
58 * x = pll_info::feedbackDiv and y = pll_info::feedbackDivFrac.
59 * (3) divided by the (integer) post divider (pll_info::postDiv).
60 * Allowed ranges are given in the pll_info min/max values.
71 pll_limit_probe(pll_info* pll)
163 pll_ppll_ss_probe(pll_info* pll, uint32 ssID)
207 pll_asic_ss_probe(pll_info* pll, uint32 ssID)
345 pll_compute_post_divider(pll_info* pl
[all...]
H A Dgpu.h184 status_t radeon_gpu_ss_control(pll_info* pll, bool enable);
H A Dmode.cpp218 pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
485 pll_info* pll = &connector->encoder.pll;
H A Daccelerant.h151 struct pll_info pll;
H A Dencoder.cpp394 pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
1333 pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
1997 pll_info* pll = &connector->encoder.pll;
H A Dgpu.cpp765 radeon_gpu_ss_control(pll_info* pll, bool enable)
H A Ddisplay.cpp998 display_crtc_ss(pll_info* pll, int command)
H A Ddisplayport.cpp650 pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/
H A Dintel_extreme.cpp765 info.shared_info->pll_info.reference_frequency = 120000;// 120 MHz
766 info.shared_info->pll_info.max_frequency = 350000;
768 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
770 info.shared_info->pll_info.reference_frequency = 96000; // 96 MHz
771 info.shared_info->pll_info.max_frequency = 400000;
773 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
775 info.shared_info->pll_info.reference_frequency = 135000;// 135 MHz
776 info.shared_info->pll_info.max_frequency = 350000;
778 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
781 info.shared_info->pll_info
[all...]
/haiku/src/add-ons/accelerants/radeon/
H A Dset_mode.h218 void Radeon_CalcPLLDividers( const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers );
220 const pll_info *pll,
226 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
228 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
H A Dpll.c52 const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers )
211 const pll_info *pll,
348 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
373 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
410 pll_info pll;
H A Dimpactv.c328 pll_info tv_pll, crt_pll;
/haiku/src/add-ons/accelerants/intel_extreme/
H A Dmode.cpp115 gInfo->shared_info->pll_info.min_frequency,
116 gInfo->shared_info->pll_info.max_frequency,
753 if (low < gInfo->shared_info->pll_info.min_frequency)
754 low = gInfo->shared_info->pll_info.min_frequency;
755 else if (low > gInfo->shared_info->pll_info.max_frequency)
762 *_high = gInfo->shared_info->pll_info.max_frequency;
H A Dpll.cpp203 pll_info &info = gInfo->shared_info->pll_info;
276 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
370 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
H A DPipes.cpp410 float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
H A Daccelerant.cpp635 info->dac_speed = gInfo->shared_info->pll_info.max_frequency;
H A DPorts.cpp2699 gInfo->shared_info->pll_info.reference_frequency,
/haiku/src/add-ons/kernel/drivers/graphics/radeon/
H A Dbios.c122 PLL_BLOCK pll, *pll_info; local
125 pll_info = (PLL_BLOCK *)(di->rom.rom_ptr + *(uint16 *)(bios_header + 0x30));
173 memcpy( &pll, pll_info, sizeof( pll ));
/haiku/headers/private/graphics/radeon/
H A Dradeon_interface.h346 } pll_info; typedef in typeref:struct:__anon22
/haiku/headers/private/graphics/intel_extreme/
H A Dintel_extreme.h272 struct pll_info { struct
473 struct pll_info pll_info; member in struct:intel_shared_info

Completed in 335 milliseconds