/haiku/src/tests/add-ons/accelerants/intel_extreme/ |
H A D | PllTest.cpp | 90 gInfo->shared_info->pll_info.reference_frequency = 120000; 91 gInfo->shared_info->pll_info.max_frequency = 350000; 92 gInfo->shared_info->pll_info.min_frequency = 20000; 96 gInfo->shared_info->pll_info.reference_frequency = 96000; 97 gInfo->shared_info->pll_info.max_frequency = 400000; 98 gInfo->shared_info->pll_info.min_frequency = 20000; 101 gInfo->shared_info->pll_info.reference_frequency = 96000; 102 gInfo->shared_info->pll_info.max_frequency = 400000; 103 gInfo->shared_info->pll_info.min_frequency = 20000; 113 gInfo->shared_info->pll_info [all...] |
/haiku/src/add-ons/accelerants/radeon_hd/ |
H A D | pll.h | 48 struct pll_info { struct 108 status_t pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID); 113 status_t pll_compute(pll_info* pll); 114 void pll_setup_flags(pll_info* pll, uint8 crtcID); 115 status_t pll_limit_probe(pll_info* pll); 116 status_t pll_ppll_ss_probe(pll_info* pll, uint32 ssID); 117 status_t pll_asic_ss_probe(pll_info* pll, uint32 ssID);
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H A D | display.h | 24 void display_crtc_ss(pll_info* pll, int command);
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H A D | pll.cpp | 52 * The reference clock signal frequency is pll_info::referenceFreq (in kHz). 54 * (1) divided by the (integer) reference divider (pll_info::referenceDiv). 58 * x = pll_info::feedbackDiv and y = pll_info::feedbackDivFrac. 59 * (3) divided by the (integer) post divider (pll_info::postDiv). 60 * Allowed ranges are given in the pll_info min/max values. 71 pll_limit_probe(pll_info* pll) 163 pll_ppll_ss_probe(pll_info* pll, uint32 ssID) 207 pll_asic_ss_probe(pll_info* pll, uint32 ssID) 345 pll_compute_post_divider(pll_info* pl [all...] |
H A D | gpu.h | 184 status_t radeon_gpu_ss_control(pll_info* pll, bool enable);
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H A D | mode.cpp | 218 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 485 pll_info* pll = &connector->encoder.pll;
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H A D | accelerant.h | 151 struct pll_info pll;
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H A D | encoder.cpp | 394 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 1333 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 1997 pll_info* pll = &connector->encoder.pll;
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H A D | gpu.cpp | 765 radeon_gpu_ss_control(pll_info* pll, bool enable)
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H A D | display.cpp | 998 display_crtc_ss(pll_info* pll, int command)
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H A D | displayport.cpp | 650 pll_info* pll = &gConnector[connectorIndex]->encoder.pll;
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/haiku/src/add-ons/kernel/drivers/graphics/intel_extreme/ |
H A D | intel_extreme.cpp | 765 info.shared_info->pll_info.reference_frequency = 120000;// 120 MHz 766 info.shared_info->pll_info.max_frequency = 350000; 768 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz 770 info.shared_info->pll_info.reference_frequency = 96000; // 96 MHz 771 info.shared_info->pll_info.max_frequency = 400000; 773 info.shared_info->pll_info.min_frequency = 20000; // 20 MHz 775 info.shared_info->pll_info.reference_frequency = 135000;// 135 MHz 776 info.shared_info->pll_info.max_frequency = 350000; 778 info.shared_info->pll_info.min_frequency = 25000; // 25 MHz 781 info.shared_info->pll_info [all...] |
/haiku/src/add-ons/accelerants/radeon/ |
H A D | set_mode.h | 218 void Radeon_CalcPLLDividers( const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers ); 220 const pll_info *pll, 226 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, 228 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll,
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H A D | pll.c | 52 const pll_info *pll, uint32 freq, uint fixed_post_div, pll_dividers *dividers ) 211 const pll_info *pll, 348 void Radeon_GetTVPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, 373 void Radeon_GetTVCRTPLLConfiguration( const general_pll_info *general_pll, pll_info *pll, 410 pll_info pll;
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H A D | impactv.c | 328 pll_info tv_pll, crt_pll;
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/haiku/src/add-ons/accelerants/intel_extreme/ |
H A D | mode.cpp | 115 gInfo->shared_info->pll_info.min_frequency, 116 gInfo->shared_info->pll_info.max_frequency, 753 if (low < gInfo->shared_info->pll_info.min_frequency) 754 low = gInfo->shared_info->pll_info.min_frequency; 755 else if (low > gInfo->shared_info->pll_info.max_frequency) 762 *_high = gInfo->shared_info->pll_info.max_frequency;
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H A D | pll.cpp | 203 pll_info &info = gInfo->shared_info->pll_info; 276 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; 370 = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
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H A D | Pipes.cpp | 410 float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f;
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H A D | accelerant.cpp | 635 info->dac_speed = gInfo->shared_info->pll_info.max_frequency;
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H A D | Ports.cpp | 2699 gInfo->shared_info->pll_info.reference_frequency,
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/haiku/src/add-ons/kernel/drivers/graphics/radeon/ |
H A D | bios.c | 122 PLL_BLOCK pll, *pll_info; local 125 pll_info = (PLL_BLOCK *)(di->rom.rom_ptr + *(uint16 *)(bios_header + 0x30)); 173 memcpy( &pll, pll_info, sizeof( pll ));
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/haiku/headers/private/graphics/radeon/ |
H A D | radeon_interface.h | 346 } pll_info; typedef in typeref:struct:__anon22
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/haiku/headers/private/graphics/intel_extreme/ |
H A D | intel_extreme.h | 272 struct pll_info { struct 473 struct pll_info pll_info; member in struct:intel_shared_info
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