Searched refs:pipe_offset (Results 1 - 9 of 9) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/irq/dce110/
H A Dirq_service_dce110.c212 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; local
215 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
/linux-master/drivers/gpu/drm/radeon/
H A Devergreen.c1832 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local
1873 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1876 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
2168 u32 pipe_offset = radeon_crtc->crtc_id * 16; local
2287 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2291 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2292 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2296 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2299 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2300 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
[all...]
H A Dsi.c1953 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local
1983 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1986 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
H A Dcik.c8805 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local
8837 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8840 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c81 int pipe_offset = (mec * dqm->dev->kfd->shared_resources.num_pipe_per_mec local
86 if (test_bit(pipe_offset + i,
1420 int pipe_offset = pipe * get_queues_per_pipe(dqm); local
1423 if (test_bit(pipe_offset + queue,
3219 int pipe_offset = pipe * get_queues_per_pipe(dqm); local
3222 if (!test_bit(pipe_offset + queue,
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v11_0.c631 u32 pipe_offset = amdgpu_crtc->crtc_id; local
664 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
666 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
669 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
H A Ddce_v10_0.c599 u32 pipe_offset = amdgpu_crtc->crtc_id; local
632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
H A Ddce_v8_0.c554 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local
587 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
590 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
H A Ddce_v6_0.c1015 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local
1045 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1048 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &

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