Searched refs:phy_write (Results 1 - 25 of 82) sorted by relevance

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/linux-master/drivers/net/phy/
H A Dvitesse.c99 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
108 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
134 phy_write(phydev, 0x1f, 0x2a30);
136 phy_write(phydev, 0x1f, 0x0000);
150 phy_write(phydev, 0x1f, 0x2a30);
152 phy_write(phydev, 0x1f, 0x52b5);
153 phy_write(phydev, 0x10, 0xb68a);
156 phy_write(phydev, 0x10, 0x968a);
157 phy_write(phydev, 0x1f, 0x2a30);
159 phy_write(phyde
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H A Dnational.c54 phy_write(phydev, NS_EXP_MEM_ADD, reg);
60 phy_write(phydev, NS_EXP_MEM_ADD, reg);
61 phy_write(phydev, NS_EXP_MEM_DATA, data);
73 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
92 phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
108 err = phy_write(phydev, DP83865_INT_MASK,
111 err = phy_write(phydev, DP83865_INT_MASK, 0);
125 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
128 phy_write(phydev, NS_EXP_MEM_CTL, 0);
129 phy_write(phyde
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H A Drockchip.c47 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
51 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
55 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_ENABLE);
61 return phy_write(phydev, SMI_ADDR_TSTCNTL, TSTMODE_DISABLE);
76 ret = phy_write(phydev, SMI_ADDR_TSTWRITE, 0xB);
79 ret = phy_write(phydev, SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG);
98 ret = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
147 err = phy_write(phydev, MII_INTERNAL_CTRL_STATUS, val);
H A Dmeson-gxl.c48 ret = phy_write(phydev, TSTCNTL, 0);
51 ret = phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
54 ret = phy_write(phydev, TSTCNTL, 0);
57 return phy_write(phydev, TSTCNTL, TSTCNTL_TEST_MODE);
62 phy_write(phydev, TSTCNTL, 0);
74 ret = phy_write(phydev, TSTCNTL, TSTCNTL_READ |
98 ret = phy_write(phydev, TSTWRITE, value);
102 ret = phy_write(phydev, TSTCNTL, TSTCNTL_WRITE |
H A Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg);
37 err = phy_write(phydev, MII_BCM63XX_IR, reg);
60 err = phy_write(phydev, MII_BCM63XX_IR, reg);
69 return phy_write(phydev, MII_BCM63XX_IR, reg);
H A Ddavicom.c87 err = phy_write(phydev, MII_DM9161_INTR, temp);
90 err = phy_write(phydev, MII_DM9161_INTR, temp);
123 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
142 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
159 err = phy_write(phydev, MII_DM9161_SCR, temp);
164 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT);
170 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
H A Dcicada.c67 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT,
73 err = phy_write(phydev, MII_CIS8201_EXT_CON1,
95 err = phy_write(phydev, MII_CIS8201_IMASK,
98 err = phy_write(phydev, MII_CIS8201_IMASK, 0);
H A Ddp83tc811.c217 err = phy_write(phydev, MII_DP83811_INT_STAT1, misr_status);
232 err = phy_write(phydev, MII_DP83811_INT_STAT2, misr_status);
244 err = phy_write(phydev, MII_DP83811_INT_STAT3, misr_status);
247 err = phy_write(phydev, MII_DP83811_INT_STAT1, 0);
251 err = phy_write(phydev, MII_DP83811_INT_STAT2, 0);
255 err = phy_write(phydev, MII_DP83811_INT_STAT3, 0);
316 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
321 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
337 err = phy_write(phydev, MII_DP83811_SGMII_CTRL,
340 err = phy_write(phyde
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H A Dmicrochip.c40 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
42 rc = phy_write(phydev, LAN88XX_INT_MASK,
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
260 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
312 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
316 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
317 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
358 phy_write(phydev, LAN88XX_INT_MASK, temp);
362 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
364 phy_write(phyde
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H A Ddp83848.c77 ret = phy_write(phydev, DP83848_MISR, DP83848_INT_EN_MASK);
81 ret = phy_write(phydev, DP83848_MICR, control);
84 ret = phy_write(phydev, DP83848_MICR, control);
H A Dqsemi.c71 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0);
110 err = phy_write(phydev, MII_QS6612_IMR,
113 err = phy_write(phydev, MII_QS6612_IMR, 0);
H A Dste10Xp.c40 err = phy_write(phydev, MII_BMCR, value);
72 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK);
74 err = phy_write(phydev, MII_XIE, 0);
H A Det1011c.c56 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
76 phy_write(phydev, ET1011C_CONFIG_REG, val |
H A Damd.c61 err = phy_write(phydev, MII_AM79C_IR, MII_AM79C_IR_IMASK_INIT);
63 err = phy_write(phydev, MII_AM79C_IR, 0);
H A Dlxt.c88 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
90 err = phy_write(phydev, MII_LXT970_IER, 0);
129 return phy_write(phydev, MII_LXT970_CONFIG, 0);
152 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
154 err = phy_write(phydev, MII_LXT971_IER, 0);
292 phy_write(phydev, MII_BMCR, val);
H A Ddp83869.c209 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
211 err = phy_write(phydev, MII_DP83869_MICR, micr_status);
337 return phy_write(phydev, MII_DP83869_MICR, val_micr);
622 ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
712 ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
722 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
727 ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
749 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
760 ret = phy_write(phydev, MII_DP83869_PHYCTRL,
766 ret = phy_write(phyde
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H A Dbcm7xxx.c79 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
107 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
265 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_BIAS_TRIM, 0x3BE0);
270 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
280 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
336 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
340 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
346 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_ADDR_CTRL,
350 ret = phy_write(phydev, MII_BCM7XXX_SHD_2_CTRL_STAT,
355 ret = phy_write(phyde
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/linux-master/drivers/net/ethernet/ibm/emac/
H A Dphy.c33 #define phy_write _phy_write macro
63 phy_write(phy, MII_BMCR, val);
74 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
126 phy_write(phy, MII_BMCR, ctl);
146 phy_write(phy, MII_ADVERTISE, adv);
158 phy_write(phy, MII_CTRL1000, adv);
164 phy_write(phy, MII_BMCR, ctl);
184 phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
201 phy_write(phy, MII_BMCR, ctl);
331 phy_write(ph
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/linux-master/arch/arm/mach-imx/
H A Dmach-imx7d.c20 phy_write(dev, 0x1e, 0x21);
21 phy_write(dev, 0x1f, 0x7ea8);
22 phy_write(dev, 0x1e, 0x2f);
23 phy_write(dev, 0x1f, 0x71b7);
H A Dmach-imx6q.c28 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
30 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
33 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
35 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
36 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
/linux-master/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c285 phy_write(phydev, 0x1f, 0x0001);
287 phy_write(phydev, 0x10, 0xf41b);
288 phy_write(phydev, 0x1f, 0x0000);
300 phy_write(phydev, 0x1d, 0x0f00);
438 phy_write(phydev, 0x1f, 0x0005);
439 phy_write(phydev, 0x05, 0x001b);
441 phy_write(phydev, 0x1f, 0x0000);
455 phy_write(phydev, 0x1f, 0x0002);
468 phy_write(phydev, 0x0d, val | set[i]);
481 phy_write(phyde
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H A Dr8169_firmware.h21 rtl_fw_write_t phy_write; member in struct:rtl_fw
/linux-master/include/linux/dsa/
H A Dlan9303.h9 int (*phy_write)(struct lan9303 *chip, int port, member in struct:lan9303_phy_ops
/linux-master/arch/powerpc/platforms/85xx/
H A Dmpc85xx_mds.c67 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
72 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
82 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
93 err = phy_write(phydev,29, 0x0006);
104 err = phy_write(phydev,30, temp);
109 err = phy_write(phydev,29, 0x000a);
126 err = phy_write(phydev,30,temp);
138 err = phy_write(phydev,16,temp);
/linux-master/drivers/phy/freescale/
H A Dphy-fsl-imx8-mipi-dphy.c142 static int phy_write(struct phy *phy, u32 value, unsigned int reg) function
324 phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);
325 phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);
326 phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);
327 phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);
328 phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);
329 phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);
330 phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);
346 phy_write(phy, CM(priv->cfg.cm), DPHY_CM);
347 phy_write(ph
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