Searched refs:phase (Results 1 - 25 of 245) sorted by relevance

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/linux-master/drivers/clk/hisilicon/
H A Dclk-hisi-phase.c5 * Simple HiSilicon phase clock implementation.
30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, argument
35 for (i = 0; i < phase->phase_num; i++)
36 if (phase->phase_regvals[i] == regval)
37 return phase->phase_degrees[i];
44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); local
47 regval = readl(phase->reg);
48 regval = (regval & phase->mask) >> phase->shift;
50 return hisi_phase_regval_to_degrees(phase, regva
53 hisi_phase_degrees_to_regval(struct clk_hisi_phase *phase, int degrees) argument
67 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); local
97 struct clk_hisi_phase *phase; local
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/linux-master/drivers/clk/sunxi-ng/
H A Dccu_phase.c15 struct ccu_phase *phase = hw_to_ccu_phase(hw); local
22 reg = readl(phase->common.base + phase->common.reg);
23 delay = (reg >> phase->shift);
24 delay &= (1 << phase->width) - 1;
58 struct ccu_phase *phase = hw_to_ccu_phase(hw); local
110 spin_lock_irqsave(phase->common.lock, flags);
111 reg = readl(phase->common.base + phase->common.reg);
112 reg &= ~GENMASK(phase
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c53 int phase; local
57 * program DPP DTO phase and modulo as below
58 * phase = ceiling(dpp_pipe_clk_mhz / 10)
64 * ceiling phase and truncate modulo guarentees the divided
67 phase = (req_dppclk + 9999) / 10000;
69 if (phase > modulo) {
70 /* phase > modulo result in screen corruption
71 * ie phase = 30, mod = 29 for 4k@60 HDMI
74 phase = modulo;
78 * set phase t
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/linux-master/fs/bcachefs/
H A Dbtree_gc.h35 /* Position of (the start of) a gc phase: */
36 static inline struct gc_pos gc_phase(enum gc_phase phase) argument
39 .phase = phase,
47 return cmp_int(l.phase, r.phase) ?:
67 .phase = btree_id_to_gc_phase(id),
/linux-master/drivers/clk/sunxi/
H A Dclk-mod0.c173 struct mmc_phase *phase = to_mmc_phase(hw); local
179 value = readl(phase->reg);
180 delay = (value >> phase->offset) & 0x3;
215 struct mmc_phase *phase = to_mmc_phase(hw); local
266 spin_lock_irqsave(phase->lock, flags);
267 value = readl(phase->reg);
268 value &= ~GENMASK(phase->offset + 3, phase->offset);
269 value |= delay << phase->offset;
270 writel(value, phase
324 struct mmc_phase *phase; local
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/linux-master/drivers/hwmon/pmbus/
H A Dmp2856.c113 mp2856_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, argument
116 int ret = pmbus_read_word_data(client, page, phase, reg);
123 int phase, u8 reg)
127 ret = mp2856_read_word_helper(client, page, phase, reg,
141 int page, int phase, u8 reg)
146 ret = pmbus_read_word_data(client, page, phase, reg);
150 if (!((phase + 1) % MP2856_PAGE_NUM))
164 int page, int phase)
169 switch (phase) {
171 ret = mp2856_read_phase(client, data, page, phase,
122 mp2856_read_vout(struct i2c_client *client, struct mp2856_data *data, int page, int phase, u8 reg) argument
140 mp2856_read_phase(struct i2c_client *client, struct mp2856_data *data, int page, int phase, u8 reg) argument
163 mp2856_read_phases(struct i2c_client *client, struct mp2856_data *data, int page, int phase) argument
207 mp2856_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
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H A Dmp2888.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
83 * Obtain resolution selector for total and phase current report and protection.
84 * 0: original resolution; 1: half resolution (in such case phase current value should
94 mp2888_read_phase(struct i2c_client *client, struct mp2888_data *data, int page, int phase, u8 reg) argument
98 ret = pmbus_read_word_data(client, page, phase, reg);
102 if (!((phase + 1) % 2))
113 * - Rcs is the internal phase current sense resistor. This parameter depends on hardware
116 * If phase current resolution bit is set to 1, READ_CSx value should be doubled.
117 * Note, that current phase sensing, providing by the device is not accurate. This is
128 mp2888_read_phases(struct i2c_client *client, struct mp2888_data *data, int page, int phase) argument
154 mp2888_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
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H A Dir35221.c25 int phase, int reg)
31 ret = pmbus_read_word_data(client, page, phase,
35 ret = pmbus_read_word_data(client, page, phase,
39 ret = pmbus_read_word_data(client, page, phase,
43 ret = pmbus_read_word_data(client, page, phase,
47 ret = pmbus_read_word_data(client, page, phase,
51 ret = pmbus_read_word_data(client, page, phase,
55 ret = pmbus_read_word_data(client, page, phase,
59 ret = pmbus_read_word_data(client, page, phase,
24 ir35221_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
H A Dlt7182s.c35 static int lt7182s_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
42 ret = pmbus_read_word_data(client, page, phase, MFR_READ_ITH);
44 ret = pmbus_read_word_data(client, 0, phase, MFR_READ_EXTVCC);
47 ret = pmbus_read_word_data(client, page, phase, MFR_IOUT_PEAK);
50 ret = pmbus_read_word_data(client, page, phase, MFR_VOUT_PEAK);
53 ret = pmbus_read_word_data(client, page, phase, MFR_VIN_PEAK);
56 ret = pmbus_read_word_data(client, page, phase, MFR_TEMPERATURE_1_PEAK);
H A Dltc3815.c73 int phase, int reg)
79 ret = pmbus_read_word_data(client, page, phase,
83 ret = pmbus_read_word_data(client, page, phase,
87 ret = pmbus_read_word_data(client, page, phase,
91 ret = pmbus_read_word_data(client, page, phase,
95 ret = pmbus_read_word_data(client, page, phase,
72 ltc3815_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
H A Dmax16064.c19 int phase, int reg)
25 ret = pmbus_read_word_data(client, page, phase,
29 ret = pmbus_read_word_data(client, page, phase,
18 max16064_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
H A Dpli1209bc.c26 int phase, int reg)
33 data = pmbus_read_word_data(client, page, phase, reg);
45 data = pmbus_read_word_data(client, page, phase,
51 return pmbus_read_word_data(client, page, phase, reg);
25 pli1209bc_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
H A Dmp2975.c3 * Hardware monitoring driver for MPS Multi-phase Digital VR Controllers
145 mp2975_read_word_helper(struct i2c_client *client, int page, int phase, u8 reg, argument
148 int ret = pmbus_read_word_data(client, page, phase, reg);
212 int page, int phase, u8 reg)
216 ret = pmbus_read_word_data(client, page, phase, reg);
220 if (!((phase + 1) % MP2975_PAGE_NUM))
231 * - Rcs is the internal phase current sense resistor which is constant
237 * Current phase sensing, providing by the device is not accurate
240 * case phase current is represented as the maximum between the value
243 ret = pmbus_read_word_data(client, page, phase, PMBUS_READ_IOU
211 mp2975_read_phase(struct i2c_client *client, struct mp2975_data *data, int page, int phase, u8 reg) argument
252 mp2975_read_phases(struct i2c_client *client, struct mp2975_data *data, int page, int phase) argument
307 mp2973_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
395 mp2975_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
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H A Dpm6764tr.c16 static int pm6764tr_read_word_data(struct i2c_client *client, int page, int phase, int reg) argument
22 ret = pmbus_read_word_data(client, page, phase, PM6764TR_PMBUS_READ_VOUT);
/linux-master/drivers/gpu/drm/tidss/
H A Dtidss_dispc_regs.h120 #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4)
122 #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4)
125 #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4)
127 #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4)
130 #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) *
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c53 int modulo, phase; local
55 // phase / modulo = dpp pipe clk / dpp global clk
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
59 if (phase > 0xff) {
61 phase = 0xff;
65 DPPCLK0_DTO_PHASE, phase,
/linux-master/lib/zstd/compress/
H A Dzstd_cwksp.h153 ZSTD_cwksp_alloc_phase_e phase; member in struct:__anon211
268 * Moves the cwksp to the next phase, and does any necessary allocations.
269 * cwksp initialization must necessarily go through each phase in order.
273 ZSTD_cwksp_internal_advance_phase(ZSTD_cwksp* ws, ZSTD_cwksp_alloc_phase_e phase) argument
275 assert(phase >= ws->phase);
276 if (phase > ws->phase) {
278 if (ws->phase < ZSTD_cwksp_alloc_buffers &&
279 phase >
324 ZSTD_cwksp_reserve_internal(ZSTD_cwksp* ws, size_t bytes, ZSTD_cwksp_alloc_phase_e phase) argument
364 const ZSTD_cwksp_alloc_phase_e phase = ZSTD_cwksp_alloc_aligned; local
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/linux-master/drivers/leds/trigger/
H A Dledtrig-heartbeat.c27 unsigned int phase; member in struct:heartbeat_trig_data
52 switch (heartbeat_data->phase) {
65 heartbeat_data->phase++;
71 heartbeat_data->phase++;
77 heartbeat_data->phase++;
84 heartbeat_data->phase = 0;
140 heartbeat_data->phase = 0;
/linux-master/drivers/net/wwan/iosm/
H A Diosm_ipc_imem_ops.c19 ipc_imem_phase_get_string(ipc_imem->phase), if_id);
21 /* The network interface is only supported in the runtime phase. */
23 dev_err(ipc_imem->dev, "net:%d : refused phase %s", if_id,
24 ipc_imem_phase_get_string(ipc_imem->phase));
66 if (ipc_imem->phase != IPC_P_RUN) {
67 dev_dbg(ipc_imem->dev, "phase %s transmit",
68 ipc_imem_phase_get_string(ipc_imem->phase));
146 enum ipc_phase phase; local
148 /* Update the current operation phase. */
149 phase
349 enum ipc_phase phase; local
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/linux-master/include/trace/events/
H A Dclk.h200 TP_PROTO(struct clk_core *core, int phase),
202 TP_ARGS(core, phase),
206 __field( int, phase )
211 __entry->phase = phase;
214 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
219 TP_PROTO(struct clk_core *core, int phase),
221 TP_ARGS(core, phase)
226 TP_PROTO(struct clk_core *core, int phase),
228 TP_ARGS(core, phase)
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/linux-master/drivers/clk/meson/
H A Dclk-phase.c11 #include "clk-phase.h"
40 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); local
43 val = meson_parm_read(clk->map, &phase->ph);
45 return meson_clk_degrees_from_val(val, phase->ph.width);
51 struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); local
54 val = meson_clk_degrees_to_val(degrees, phase->ph.width);
55 meson_parm_write(clk->map, &phase->ph, val);
68 * The phase of mst_sclk clock output can be controlled independently
72 * If necessary, we can still control the phase in the tdm block
87 /* Get phase
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/linux-master/drivers/char/ipmi/
H A Dkcs_bmc_cdev_ipmi.c76 enum kcs_ipmi_phases phase; member in struct:kcs_bmc_ipmi
133 priv->phase = KCS_PHASE_ERROR;
145 switch (priv->phase) {
147 priv->phase = KCS_PHASE_WRITE_DATA;
165 priv->phase = KCS_PHASE_WRITE_DONE;
187 priv->phase = KCS_PHASE_IDLE;
198 priv->phase = KCS_PHASE_ABORT_ERROR2;
205 priv->phase = KCS_PHASE_IDLE;
224 priv->phase = KCS_PHASE_WRITE_START;
231 if (priv->phase !
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/linux-master/drivers/char/
H A Dppdev.c20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
37 * GETPHASE gets the current IEEE1284 phase
397 pp->saved_state.phase = info->phase;
399 info->phase = pp->state.phase;
428 pp->state.phase = init_phase(mode);
432 pp->pdev->port->ieee1284.phase = pp->state.phase;
452 int phase; local
467 int phase; local
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/linux-master/drivers/gpu/drm/imx/dcss/
H A Ddcss-scaler.c178 int phase; local
183 for (phase = 0; phase < PSC_STORED_PHASES; phase++) {
184 coef[phase][0] = 0;
185 coef[phase][PSC_NUM_TAPS - 1] = 0;
225 /* override phase 0 with identity filter if specified */
232 for (phase = 0; phase < PSC_STORED_PHASES; phase
574 int i, phase; local
609 int i, phase; local
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/linux-master/drivers/parport/
H A Dieee1284_ops.c52 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
138 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
171 port->ieee1284.phase = IEEE1284_PH_REV_DATA;
217 /* Go to reverse idle phase. */
221 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
224 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL;
259 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA;
302 /* Go to reverse idle phase. */
306 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE;
309 port->physport->ieee1284.phase
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