Searched refs:patched_crtc_timing (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.c163 struct dc_crtc_timing patched_crtc_timing; local
180 patched_crtc_timing = *dc_crtc_timing;
181 apply_front_porch_workaround(&patched_crtc_timing);
182 optc1->orginal_patched_timing = patched_crtc_timing;
188 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
193 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
196 asic_blank_start = patched_crtc_timing.h_total -
197 patched_crtc_timing.h_front_porch;
201 patched_crtc_timing.h_border_right -
202 patched_crtc_timing
343 struct dc_crtc_timing patched_crtc_timing; local
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c286 struct dc_crtc_timing patched_crtc_timing; local
303 patched_crtc_timing = *dc_crtc_timing;
305 dce110_timing_generator_apply_front_porch_workaround(tg, &patched_crtc_timing);
309 bp_params.h_total = patched_crtc_timing.h_total;
311 patched_crtc_timing.h_addressable;
312 bp_params.v_total = patched_crtc_timing.v_total;
313 bp_params.v_addressable = patched_crtc_timing.v_addressable;
316 bp_params.h_sync_width = patched_crtc_timing.h_sync_width;
318 bp_params.v_sync_width = patched_crtc_timing.v_sync_width;
322 patched_crtc_timing
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1110 struct dc_crtc_timing patched_crtc_timing; local
1115 patched_crtc_timing = *dc_crtc_timing;
1117 if (patched_crtc_timing.flags.INTERLACE == 1) {
1118 if (patched_crtc_timing.v_front_porch < 2)
1119 patched_crtc_timing.v_front_porch = 2;
1121 if (patched_crtc_timing.v_front_porch < 1)
1122 patched_crtc_timing.v_front_porch = 1;
1126 asic_blank_start = patched_crtc_timing.v_total -
1127 patched_crtc_timing.v_front_porch;
1131 patched_crtc_timing
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/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1607 struct dc_crtc_timing patched_crtc_timing; local
1612 patched_crtc_timing = *dc_crtc_timing;
1614 if (patched_crtc_timing.flags.INTERLACE == 1) {
1615 if (patched_crtc_timing.v_front_porch < 2)
1616 patched_crtc_timing.v_front_porch = 2;
1618 if (patched_crtc_timing.v_front_porch < 1)
1619 patched_crtc_timing.v_front_porch = 1;
1623 asic_blank_start = patched_crtc_timing.v_total -
1624 patched_crtc_timing.v_front_porch;
1628 patched_crtc_timing
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c3778 struct dc_crtc_timing patched_crtc_timing; local
3783 patched_crtc_timing = *dc_crtc_timing;
3784 apply_front_porch_workaround(&patched_crtc_timing);
3786 interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
3788 vesa_sync_start = patched_crtc_timing.v_addressable +
3789 patched_crtc_timing.v_border_bottom +
3790 patched_crtc_timing.v_front_porch;
3792 asic_blank_end = (patched_crtc_timing.v_total -
3794 patched_crtc_timing.v_border_top)

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